# US 2021/0280776 A1 · Reducing parasitic bottom electrode resistance of embedded mram

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- Number: US 2021/0280776 A1
- Document ID: US20210280776A1
- Status: Published application
- Kind: A1
- Application number: 16/809,916
- Filed: 2020-03-05
- Published: 2021-09-09
- Earliest claimed: 2020-03-05
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Julien Frougier; Ruilong Xie; Alexander Reznicek; Bruce B. Doris
- Web page: https://patentgrep.com/patent/US20210280776A1

## CPC

- H10N 50/10: Magnetoresistive devices
- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10N 50/01: Manufacture or treatment
- H10N 50/80: Constructional details
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

An embedded magnetoresistive random-access memory (MRAM) device including a portion of a metal wiring layer above a semiconductor device and a bottom electrode over the portion of the metal wiring layer. The embedded MRAM where the bottom electrode connects to a first portion of a bottom surface of a magnetoresistive random access memory pillar and a sidewall spacer is on the magnetoresistive random access memory pillar. The embedded MRAM device includes a ring of inner metal is on the portion of the metal wiring layer surrounding a portion of the bottom electrode.

## Claims

### Claim 1

An embedded magnetoresistive random-access memory (MRAM) device, comprising:
a portion of a metal wiring layer above a semiconductor device;
a bottom electrode over the portion of the metal wiring layer connects to a first portion of a bottom surface of a magnetoresistive random access memory pillar, wherein a sidewall spacer is on the magnetoresistive random access memory pillar; and
a ring of inner metal is on the portion of the metal wiring layer surrounding a portion of the bottom electrode.

### Claim 2 (depends on 1)

The embedded MRAM device of claim 1, wherein the portion of the metal wiring layer is embedded in a first interlayer dielectric and is on a first metal contact to the semiconductor device.

### Claim 3 (depends on 2)

The embedded MRAM device of claim 2, further comprising:
a second metal contact on the magnetoresistive random access memory pillar abuts a portion of a second interlayer dielectric material and a portion of the sidewall spacer on the magnetoresistive random access memory pillar; and
the second interlayer dielectric material is on the first interlayer dielectric surrounding a portion of the ring of inner metal, around the sidewall spacer on the magnetoresistive random access memory pillar, and around the second metal contact on the magnetoresistive random access memory pillar.

### Claim 4 (depends on 1)

The embedded MRAM device of claim 1, wherein the ring of inner metal surrounding the portion of the bottom electrode provides a reduction of an electrical resistance of the bottom electrode.

### Claim 5 (depends on 1)

The embedded MRAM device of claim 1, wherein the ring of inner metal surrounds the portion of the bottom electrode increasing an effective size of the bottom electrode.

### Claim 6 (depends on 1)

The embedded MRAM device of claim 1, wherein a width of the bottom electrode over the portion of the metal wiring layer is less than a width of the magnetoresistive random access memory pillar.

### Claim 7 (depends on 1)

The embedded MRAM device of claim 1, wherein the ring of inner metal surrounding the portion of the bottom electrode is under a dielectric layer that is under a second portion of the bottom surface of a magnetoresistive random access memory pillar.

### Claim 8 (depends on 7)

The embedded MRAM device of claim 7, wherein the ring of inner metal surrounding the portion of the bottom electrode is under the sidewall spacer of the magnetoresistive random access memory pillar and under the dielectric layer under the second portion of the bottom surface of a magnetoresistive random access memory pillar.

### Claim 9 (depends on 8)

The embedded MRAM device of claim 8, wherein the ring of inner metal surrounding the portion of the bottom electrode is a solid metal ring when a width of the ring of inner metal adjacent to the dielectric layer is less than a thickness of the ring of inner metal under the sidewall spacer.

### Claim 10 (depends on 8)

The embedded MRAM device of claim 8, wherein the ring of inner metal surrounding the portion of the bottom electrode has an air gap inside a center portion of the ring of inner metal when a width of the ring of inner metal adjacent to the dielectric layer is greater than a thickness of the ring of inner metal under the sidewall spacer.

### Claim 11

A method of forming an embedded magnetoresistive random-access memory (MRAM) device, comprising:
depositing a sacrificial layer over a first interlayer dielectric and a portion of a metal wiring layer over a semiconductor device;
depositing a dielectric layer over a top surface of the sacrificial layer;
forming a bottom metal electrode over the portion of the metal layer in the semiconductor device;
depositing a magnetic tunnel junction (MTJ) stack covered by a hardmask;
etching a portion of the MTJ stack, a portion of the hardmask, a first portion of the dielectric layer, and a first portion of the sacrificial layer;
forming a sidewall spacer around the MTJ stack, around a remaining portion of the dielectric layer, and around a remaining portion of the sacrificial layer;
removing the remaining portion of the sacrificial layer;
depositing an inner metal over the portion of the metal layer in the semiconductor device, around the bottom metal electrode, and over an exposed bottom surface of the remaining portion of the dielectric layer; and
selectively etching exposed portions of the inner metal to form a ring of inner metal around a portion of the bottom metal electrode.

### Claim 12 (depends on 11)

The method of forming the embedded MRAM device of claim 11, wherein depositing the inner metal includes using a conformal deposition process.

### Claim 13 (depends on 11)

The method of forming the embedded MRAM device of claim 11, wherein selectively etching the portion of the MTJ stack includes an anisotropic etch of a portion of a capping layer, a portion of a free layer, a portion of a tunneling barrier layer, a portion of a reference layer.

### Claim 14 (depends on 11)

The method of forming the embedded MRAM device of claim 11, wherein;
forming the bottom metal electrode, comprises:
selectively etching a second portion of the dielectric layer and a second portion of the sacrificial layer over the portion of the metal layer of the semiconductor device;
depositing a layer of electrode metal over the dielectric layer and over an exposed portion of the portion of the metal layer of the semiconductor device; and
performing a chemical mechanical polish of a top surface of the layer of electrode metal until contacting the dielectric layer.

### Claim 15 (depends on 11)

The method of forming the embedded MRAM device of claim 11, wherein etching the first portion of the dielectric layer includes removing the first dielectric layer that is above a remaining portion of the sacrificial layer over the first interlayer dielectric.

### Claim 16 (depends on 11)

The method of forming the embedded MRAM device of claim 11, wherein etching the portion of the MTJ stack, the portion of the hardmask, the portion of the dielectric layer, and the portion of the sacrificial layer leaves a thickness of the remaining portion of the sacrificial layer over the first interlayer dielectric that is greater than a width of the remaining portion of the sacrificial layer between the bottom metal electrode and the sidewall spacer.

### Claim 17 (depends on 16)

The method of forming the embedded MRAM device of claim 16, further comprises depositing the inner metal forms the ring of inner metal around a bottom portion of the bottom metal electrode that is a solid metal ring.

### Claim 18 (depends on 11)

The method of forming the embedded MRAM device of claim 11, wherein etching the portion of the MTJ stack, the portion of the hardmask, the portion of the dielectric layer, and the portion of the sacrificial layer leaves a thickness of the remaining portion of the sacrificial layer over the first interlayer dielectric that is less than a width of the sacrificial layer between the bottom metal electrode and the sidewall spacer.

### Claim 19 (depends on 18)

The method of forming the embedded MRAM device of claim 18, wherein depositing the inner metal forms a hollow metal tube around a bottom portion of the bottom metal electrode, wherein the hollow metal tube includes an air gap inside the hollow metal tube.

### Claim 20 (depends on 11)

The method of forming the embedded MRAM device of claim 11, wherein etching the portion of the dielectric layer includes leaving a portion of the dielectric layer over the top surface of the sacrificial layer.