# US 2021/0280773 A1 · Via landing enhancement for memory device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2021/0280773 A1
- Document ID: US20210280773A1
- Status: Published application
- Kind: A1
- Application number: 17/319,590
- Filed: 2021-05-13
- Published: 2021-09-09
- Earliest claimed: 2018-10-23
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chun-Heng Liao; Harry-Hak-Lay Chuang; Chang-Jen Hsieh; Hung Cho Wang
- Web page: https://patentgrep.com/patent/US20210280773A1

## CPC

- H10N 50/80: Constructional details
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10N 50/01: Manufacture or treatment
- H10N 50/10: Magnetoresistive devices
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10N 70/8836: {Complex metal oxides, e.g. perovskites, spinels}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A memory cell with dual sidewall spacers and its manufacturing methods are provided. In some embodiments, the memory cell includes a bottom electrode disposed over a substrate, a resistance switching dielectric disposed over the bottom electrode and having a variable resistance, and a top electrode disposed over the resistance switching dielectric. The memory cell further includes a first sidewall spacer disposed on an upper surface of the bottom electrode and extending upwardly alongside the resistance switching dielectric and the top electrode. The memory cell further includes a second sidewall spacer having a bottom surface disposed on the upper surface of the bottom electrode and directly and conformally lining the first sidewall spacer.

## Claims

### Claim 1

A memory cell, comprising:
a bottom electrode disposed over a substrate;
a resistance switching dielectric disposed over the bottom electrode and having a variable resistance;
a top electrode disposed over the resistance switching dielectric;
a first sidewall spacer disposed on an upper surface of the bottom electrode and extending upwardly alongside the resistance switching dielectric and the top electrode; and
a second sidewall spacer having a bottom surface disposed on the upper surface of the bottom electrode and directly and conformally lining the first sidewall spacer.

### Claim 2 (depends on 1)

The memory cell of claim 1, wherein the bottom electrode has a sidewall aligned with that of the second sidewall spacer.

### Claim 3 (depends on 1)

The memory cell of claim 1, wherein a top surface of the second sidewall spacer is higher than that of the first sidewall spacer.

### Claim 4 (depends on 1)

The memory cell of claim 1, further comprising:
an upper dielectric layer surrounding the bottom electrode, the second sidewall spacer and overlying the top electrode; and
a top electrode via extending through the upper dielectric layer to reach on the top electrode.

### Claim 5 (depends on 4)

The memory cell of claim 4, wherein the top electrode via contacts the first sidewall spacer at a first interface and contacts the second sidewall spacer at a second interface higher than the first interface.

### Claim 6 (depends on 1)

The memory cell of claim 1, wherein the second sidewall spacer has a second thickness greater than at least two times of a first thickness of the first sidewall spacer.

### Claim 7 (depends on 1)

The memory cell of claim 1, wherein the second sidewall spacer and the first sidewall spacer comprise different materials or the same material with different densities.

### Claim 8

An integrated circuit comprising a memory cell, the memory cell comprising:
a bottom electrode disposed over a substrate;
a resistance switching dielectric disposed over the bottom electrode and having a variable resistance;
a top electrode disposed over the resistance switching dielectric;
a first sidewall spacer extending alongside the resistance switching dielectric and the top electrode;
a second sidewall spacer directly lining the first sidewall spacer; and
a top electrode via surrounded by an upper dielectric layer and disposed on the top electrode;
wherein the top electrode via has a bottom contacting the first sidewall spacer at a first interface and contacting the second sidewall spacer at a second interface higher than the first interface.

### Claim 9 (depends on 8)

The integrated circuit of claim 8,
wherein the top electrode via has an asymmetrical shape along an extending vertical line that bisects a top of the top electrode via; and
wherein a lower sidewall of the top electrode via at one side closer to a boundary of the memory cell is more inside tilted than the other side closer to a center region of the memory cell.

### Claim 10 (depends on 8)

The integrated circuit of claim 8, wherein the first sidewall spacer is disposed directly on an upper surface of the bottom electrode.

### Claim 11 (depends on 8)

The integrated circuit of claim 8, wherein a top surface of the second sidewall spacer is higher than that of the first sidewall spacer.

### Claim 12 (depends on 8)

The integrated circuit of claim 8, further comprising:
a lower metallization line of an interconnect structure surrounded by a bottom interlayer dielectric layer and coupled to the bottom electrode of the memory cell; and
an upper metallization line of the interconnect structure surrounded by a top interlayer dielectric layer and coupled to the top electrode of the memory cell.

### Claim 13 (depends on 8)

The integrated circuit of claim 8, wherein the second sidewall spacer is disposed on an upper surface of the bottom electrode.

### Claim 14

An integrated circuit, comprising:
a bottom electrode disposed over a substrate;
a resistance switching dielectric disposed over the bottom electrode and having a variable resistance;
a top electrode disposed over the resistance switching dielectric;
a first sidewall spacer disposed on an upper surface of the bottom electrode and extending upwardly along sidewalls of the resistance switching dielectric and the top electrode;
a second sidewall spacer directly and conformally lining the first sidewall spacer; and
a top electrode via reaching on the top electrode.

### Claim 15 (depends on 14)

The integrated circuit of claim 14, wherein the second sidewall spacer has a second thickness greater than at least two times of a first thickness the first sidewall spacer.

### Claim 16 (depends on 14)

The integrated circuit of claim 14, wherein the first sidewall spacer and the second sidewall spacer are made of silicon nitride.

### Claim 17 (depends on 14)

The integrated circuit of claim 14, wherein a top surface of the second sidewall spacer is higher than that of the first sidewall spacer.

### Claim 18 (depends on 14)

The integrated circuit of claim 14, wherein the top electrode via has a bottom surface contacting the first sidewall spacer and a sidewall surface contacting the second sidewall spacer.

### Claim 19 (depends on 14)

The integrated circuit of claim 14, further comprising:
a bottom metallization line surrounded by a bottom interlayer dielectric layer and coupled to the bottom electrode through a bottom electrode via; and
a top metallization line surrounded by a top interlayer dielectric layer and coupled to the top electrode through the top electrode via.

### Claim 20 (depends on 14)

The integrated circuit of claim 14,
wherein the first sidewall spacer directly contacts sidewalls of the resistance switching dielectric and the top electrode; and
wherein the second sidewall spacer is disposed on the upper surface of the bottom electrode, and wherein a sidewall of the second sidewall spacer is aligned with a sidewall of the bottom electrode.