# US 2021/0280722 A1 · Strained silicon transistor

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- Number: US 2021/0280722 A1
- Document ID: US20210280722A1
- Status: Published application
- Kind: A1
- Application number: 16/809,534
- Filed: 2020-03-04
- Published: 2021-09-09
- Earliest claimed: 2020-03-04
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Haining YANG; Bin YANG; Xia LI
- Web page: https://patentgrep.com/patent/US20210280722A1

## CPC

- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/502: {characterised by the stacked channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/6743: {Silicon}
- H10D 30/798: {being provided in or under the channel regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3462: {Nanowires}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/642: {Chemical etching}
- H10P 50/691: {for Group IV materials or Group III-V materials}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/364: {of IGFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Strained silicon transistor, such as GAA transistors, allow for both good PMOS mobility and NMOS mobility on the same substrate. In one example, a GAA circuit may include a NMOS device on a tensile strained Si channel and a PMOS device on a compressive strained SiGe channel. In another example, a GAA circuit may include a NMOS device on a strained Si channel and a PMOS device on a relaxed SiGe channel on (110) crystalline substrate.

## Claims

### Claim 1

A transistor circuit comprising:
a first transistor comprising a silicon channel; and
a second transistor comprising a silicon germanium channel.

### Claim 2 (depends on 1)

The transistor circuit of claim 1, wherein the first transistor is a NMOS transistor and the silicon channel is a strained silicon channel.

### Claim 3 (depends on 2)

The transistor circuit of claim 2, wherein the strained silicon channel is a tensile strained silicon channel.

### Claim 4 (depends on 1)

The transistor circuit of claim 1, wherein the second transistor is a PMOS transistor and the silicon germanium channel is a strained channel.

### Claim 5 (depends on 4)

The transistor circuit of claim 4, wherein the strained silicon germanium channel is a compressive strained silicon germanium channel.

### Claim 6 (depends on 1)

The transistor circuit of claim 1, wherein the silicon channel is a strained silicon channel and the silicon germanium channel is a relaxed silicon germanium channel.

### Claim 7 (depends on 1)

The transistor circuit of claim 1, wherein the silicon germanium channel is a on a 110 substrate.

### Claim 8 (depends on 7)

The transistor circuit of claim 7, wherein the silicon germanium channel is a relaxed silicon germanium channel.

### Claim 9 (depends on 1)

The transistor circuit of claim 1, wherein the first transistor is a NMOS transistor and the second transistor is a PMOS transistor.

### Claim 10 (depends on 1)

The transistor circuit of claim 1, wherein the transistor circuit is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle.

### Claim 11

A transistor circuit comprising:
first means for amplifying or switching comprising a silicon channel; and
second means for amplifying or switching comprising a silicon germanium channel.

### Claim 12 (depends on 11)

The transistor circuit of claim 11, wherein the first means for amplifying or switching is a NMOS transistor and the silicon channel is a strained silicon channel.

### Claim 13 (depends on 12)

The transistor circuit of claim 12, wherein the strained silicon channel is a tensile strained silicon channel.

### Claim 14 (depends on 11)

The transistor circuit of claim 11, wherein the second means for amplifying or switching is a PMOS transistor and the silicon germanium channel is a strained channel.

### Claim 15 (depends on 14)

The transistor circuit of claim 14, wherein the strained silicon germanium channel is a compressive strained silicon germanium channel.

### Claim 16 (depends on 11)

The transistor circuit of claim 11, wherein the silicon channel is a strained silicon channel and the silicon germanium channel is a relaxed silicon germanium channel.

### Claim 17 (depends on 11)

The transistor circuit of claim 11, wherein the silicon germanium channel is a on a 110 substrate.

### Claim 18 (depends on 17)

The transistor circuit of claim 17, wherein the silicon germanium channel is a relaxed silicon germanium channel.

### Claim 19 (depends on 11)

The transistor circuit of claim 11, wherein the first means for amplifying or switching is a NMOS transistor and the second means for amplifying or switching is a PMOS transistor.

### Claim 20 (depends on 11)

The transistor circuit of claim 11, wherein the transistor circuit is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle.

### Claim 21

A transistor circuit comprising:
a NMOS transistor comprising a silicon channel; and
a PMOS transistor comprising a silicon germanium channel.

### Claim 22 (depends on 21)

The transistor circuit of claim 21, wherein the silicon channel is a strained silicon channel on a 100 substrate.

### Claim 23 (depends on 22)

The transistor circuit of claim 22, wherein the strained silicon channel is a tensile strained silicon channel.

### Claim 24 (depends on 21)

The transistor circuit of claim 21, wherein the silicon germanium channel is a strained channel on a 100 substrate.

### Claim 25 (depends on 24)

The transistor circuit of claim 24, wherein the strained silicon germanium channel is a compressive strained silicon germanium channel.

### Claim 26 (depends on 21)

The transistor circuit of claim 21, wherein the silicon channel is a strained silicon channel on a 110 substrate and the silicon germanium channel is a relaxed silicon germanium channel on a 110 substrate.

### Claim 27 (depends on 21)

The transistor circuit of claim 21, wherein the transistor circuit is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle.

### Claim 28

A method of manufacturing a transistor circuit, the method comprising:
providing a substrate;
forming a plurality of alternative epitaxial layers of silicon and silicon germanium;
forming a shallow trench insolation region;
forming a dummy gate;
depositing a gate spacer;
etching the gate spacer;
etching a PMOS region;
etching the silicon germanium layers to form recessed regions;
forming a plurality of spacers in the recessed regions;
forming a source region and a drain region for the PMOS region;
forming a NMOS spacer; and
forming a source region and a drain region for an NMOS region.

### Claim 29 (depends on 28)

The method of claim 28, further comprising:
depositing a silicon nitride film before forming the shallow trench isolation region;
masking an NMOS region before etching the PMOS spacer; and
wherein the source region and the drain region for the PMOS region and the NMOS region are epitaxial grown.

### Claim 30 (depends on 28)

The method of claim 28, further comprising incorporating the transistor circuit into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle.