# US 2021/0280717 A1 · Method of fabricating semiconductor device

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- Number: US 2021/0280717 A1
- Document ID: US20210280717A1
- Status: Published application
- Kind: A1
- Application number: 17/330,443
- Filed: 2021-05-26
- Published: 2021-09-09
- Earliest claimed: 2018-10-29
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Kuang-Hsiu Chen; Sung-Yuan Tsai; Chi-Hsuan Tang; Chun-Wei Yu; Yu-Ren Wang
- Web page: https://patentgrep.com/patent/US20210280717A1

## CPC

- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 30/0223: {having source and drain regions or source and drain extensions self-aligned to sides of the gate}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/60: Impurity distributions or concentrations
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/514: {characterised by the insulating layers}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.

## Claims

### Claim 1

A method of forming a semiconductor device, comprising:
providing a substrate;
forming a gate structure on the substrate; and
forming an epitaxial structure in the substrate, at one side of the gate structure, the epitaxial structure comprising a portion being protruding from a top surface of the substrate, the portion comprising a discontinuous sidewall, wherein a distance between a turning point on the discontinuous sidewall and the gate structure is a maximum distance between the epitaxial structure and the gate structure.

### Claim 2 (depends on 1)

The method of forming the semiconductor device according to claim 1, wherein the forming of the epitaxial structure comprises:
forming a first epitaxial layer in the substrate, at the side of the gate structure, wherein the first epitaxial layer comprising a gradually shrinking portion being protruded from the top surface of the substrate;
forming a first deposition layer sandwiched between the gate structure and the first epitaxial layer, to expose a top surface of the first epitaxial layer; and
forming a second epitaxial layer from the top surface of the first epitaxial layer.

### Claim 3 (depends on 2)

The method of forming the semiconductor device according to claim 2, wherein the forming of the first epitaxial layer comprises:
forming a second deposition layer covering the gate structure, the second deposition layer comprising a tapered sidewall; and
forming the first epitaxial layer in the substrate.

### Claim 4 (depends on 3)

The method of forming the semiconductor device according to claim 3, wherein the forming of the first deposition layer further comprising:
after forming the second deposition layer, forming a material layer covering the gate structure and the first epitaxial layer; and
partially removing the material layer to expose the top surface of the first epitaxial layer, and forming the first deposition layer.

### Claim 5 (depends on 3)

The method of forming the semiconductor device according to claim 3, further comprising:
completely removing the first deposition layer and the second deposition layer, to obtain the epitaxial structure.

### Claim 6 (depends on 1)

The method of forming the semiconductor device according to claim 1, wherein the portion comprises a gradually shrinking portion and a gradually expanding portion, and the turning point is disposed between the gradually shrinking portion and the gradually expanding portion, and the gradually expanding portion covers a whole top surface of the gradually shrinking portion.