# US 2021/0280710 A1 · Device of dielectric layer

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- Number: US 2021/0280710 A1
- Document ID: US20210280710A1
- Status: Published application
- Kind: A1
- Application number: 17/327,737
- Filed: 2021-05-23
- Published: 2021-09-09
- Earliest claimed: 2017-09-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yu-Yun PENG; Keng-Chu LIN
- Web page: https://patentgrep.com/patent/US20210280710A1

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- C23C 16/045: {Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates}
- C23C 16/40: Oxides
- C23C 16/405: {of refractory metals or yttrium}
- C23C 16/45531: {specially adapted for making ternary or higher compositions}
- C23C 16/45536: {Use of plasma, radiation or electromagnetic fields}
- C23C 16/45551: {for relative movement of the substrate and the gas injectors or half-reaction reactor compartments}
- C23C 16/4584: {the substrate being rotated}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/662: {Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548)}
- H10P 14/6928: {the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides}
- H10P 14/693: {the material containing hafnium, e.g. HfSiOx or HfSiON}
- H10P 14/69391: {the material containing aluminium, e.g. Al2O3}
- H10P 14/69395: {the material containing zirconium, e.g. ZrO2}
- H10P 14/69397: {the material containing two or more metal elements}
- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/076: {in via holes or trenches}
- H10W 20/097: {by thermally treating}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10P 14/6929: {the material containing aluminium, e.g. AlSiOx}
- H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions}
- H10W 20/098: {by filling between adjacent conductive parts}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A device includes a semiconductive substrate, a fin structure, and an isolation material. The fin structure extends from the semiconductive substrate. The isolation material is over the semiconductive substrate and adjacent to the fin structure, wherein the isolation material includes a first metal element, a second metal element, and oxide.

## Claims

### Claim 1

A device comprising:
a semiconductive substrate;
a fin structure extending from the semiconductive substrate; and
an isolation material over the semiconductive substrate and adjacent to the fin structure, wherein the isolation material comprises a first metal element, a second metal element, and oxide.

### Claim 2 (depends on 1)

The device of claim 1, wherein the first metal element is Al, Mg, Ti, Zn, Zr, Y, Ta, or Hf.

### Claim 3 (depends on 2)

The device of claim 2, wherein the second metal element is Al, Mg, Ti, Zn, Zr, Y, Ta, or Hf.

### Claim 4 (depends on 1)

The device of claim 1, wherein the first metal element is aluminum, the second metal element is zirconium, and an atomic ratio of aluminum to zirconium is equal to or less than about 0.05.

### Claim 5 (depends on 1)

The device of claim 1, further comprising a liner layer between the isolation material and the fin structure.

### Claim 6 (depends on 5)

The device of claim 5, wherein the liner layer comprises the first and second metal elements.

### Claim 7 (depends on 5)

The device of claim 5, wherein the liner layer and the isolation material comprise substantially same materials.

### Claim 8

A device comprising:
a semiconductive substrate;
a gate structure over the semiconductive substrate;
an interlayer dielectric (ILD) layer over the semiconductive substrate and surrounding the gate structure; and
a dielectric liner layer between the semiconductive substrate and the ILD layer, wherein the dielectric liner layer comprises a metal element, silicon, and oxide in a form of solid solution or metastable phase.

### Claim 9 (depends on 8)

The device of claim 8, wherein the metal element is Al, Mg, Ti, Zn, Zr, Y, Ta, or Hf.

### Claim 10 (depends on 8)

The device of claim 8, wherein the metal element is hafnium, and an atomic ratio of hafnium to silicon is in a range from about 0.25 to about 1.

### Claim 11 (depends on 8)

The device of claim 8, wherein the metal element is magnesium, and an atomic ratio of silicon to magnesium is equal to or less than about 0.02.

### Claim 12 (depends on 8)

The device of claim 8, wherein the ILD layer comprises the metal element.

### Claim 13 (depends on 8)

The device of claim 8, wherein the ILD layer is in a metastable phase.

### Claim 14 (depends on 8)

The device of claim 8, further comprising a contact etch stop layer between the dielectric liner layer and the semiconductive substrate.

### Claim 15

A device comprising:
first and second source/drain features;
a gate structure between the first and second source/drain features;
an interlayer dielectric (ILD) layer over the first and second source/drain features; and
a dielectric liner layer between the gate structure and the ILD layer, wherein the ILD layer and the dielectric liner layer comprise a same first metal element.

### Claim 16 (depends on 15)

The device of claim 15, wherein both the ILD layer and the dielectric liner layer are oxide layers.

### Claim 17 (depends on 15)

The device of claim 15, wherein both the ILD layer and the dielectric liner layer further comprise silicon.

### Claim 18 (depends on 15)

The device of claim 15, wherein the ILD layer and the dielectric liner layer further comprise a same second metal element.

### Claim 19 (depends on 15)

The device of claim 15, wherein the ILD layer is in a metastable phase.

### Claim 20 (depends on 15)

The device of claim 15, wherein the dielectric liner layer is in a form of a solid solution.