# US 2021/0280708 A1 · Transistor arrangements with metal gate cuts and recessed power rails

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- Number: US 2021/0280708 A1
- Document ID: US20210280708A1
- Status: Published application
- Kind: A1
- Application number: 16/812,428
- Filed: 2020-03-09
- Published: 2021-09-09
- Earliest claimed: 2020-03-09
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Andy Chih-Hung Wei; Sean T. Ma; Piyush Mohan Sinha
- Web page: https://patentgrep.com/patent/US20210280708A1

## CPC

- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/427: {Power or ground buses}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 62/121: {oriented parallel to substrates}
- H10W 20/0698: {Local interconnections}
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Described herein are transistor arrangements fabricated by forming a metal gate cut as a trench that is non-selective to the gate sidewalls, in an etch process that can remove both the gate electrode materials and the surrounding dielectrics. Such an etch process may provide improvements in terms of accuracy, cost-efficiency, and device performance, compared to conventional approaches to forming metal gate cuts. In addition, such a process may be used to provide power rails, if the trench of a metal gate cut is to be at least partially filled with an electrically conductive material. Because the electrically conductive material is in the trench and may be in between the fins, as opposed to being provided over the fins, such power rails may be referred to as “recessed.” Providing recessed power rails may provide improvements in terms of reduced metal line resistance and reduced voltage droop.

## Claims

### Claim 1

A transistor arrangement, comprising:
a first fin, extending away from a base;
a second fin, extending away from the base, where each of the first and the second fin includes one or more semiconductor materials;
a gate electrode material having:
a first portion that at least partially wraps around an end of the first fin that is farthest away from the base, and
a second portion that at least partially wraps around an end of the second fin that is farthest away from the base; and
an opening in the gate electrode material between the first portion and the second portion, the opening at least partially filled with one or more dielectric materials,
where a distance from the base to the opening is at least 5 nanometers smaller than a distance from the base to the gate electrode material.

### Claim 2 (depends on 1)

The transistor arrangement according to claim 1, wherein the one or more dielectric materials are in contact with the gate electrode material.

### Claim 3 (depends on 2)

The transistor arrangement according to claim 2, wherein:
a portion of the first fin that is closest to the base and a portion of the second fin that is closest to the base is surrounded by a shallow trench insulator (STI) material, and
the one or more dielectric materials are in contact with the STI electrode material.

### Claim 4 (depends on 1)

The transistor arrangement according to claim 1, wherein:
the first portion of the gate electrode material forms a gate terminal of a first transistor,
the transistor further includes a further gate electrode material wrapping a further portion of the end of the first fin that is farthest away from the base, the further gate electrode material forming a gate terminal of a second transistor, and
in a direction of a longitudinal axis of the first fin, the opening extends to at least 30% of a distance between the gate terminal of the first transistor and the gate terminal of the second transistor.

### Claim 5 (depends on 4)

The transistor arrangement according to claim 4, wherein a length of the opening in the direction of the longitudinal axis of the first fin is substantially equal to a pitch between the gate terminal of the first transistor and the gate terminal of the second transistor.

### Claim 6 (depends on 4)

The transistor arrangement according to claim 4, wherein the opening includes a seam, the seam extending in a plane substantially parallel to each of the first fin and the second fin.

### Claim 7 (depends on 1)

The transistor arrangement according to claim 1, wherein:
the opening is a first opening,
the transistor arrangement further includes:
a third fin, extending away from the base, where the second fin is between the first fin and the third fin, and where the gate electrode material has a third portion that at least partially wraps around an end of the third fin that is farthest away from the base, and
a second opening in the gate electrode material between the second portion and the third portion, where the second opening is partially filled with the one or more dielectric materials and partially filled with one or more electrically conductive materials, and where the one or more electrically conductive materials are separated from the second and third portions of the gate electrode material by the one or more dielectric materials filling the opening.

### Claim 8 (depends on 7)

The transistor arrangement according to claim 7, wherein an aspect ratio of the second opening is between 2 and 1.

### Claim 9 (depends on 7)

The transistor arrangement according to claim 7, wherein an aspect ratio of the second opening is equal or smaller than an aspect ratio of the first opening.

### Claim 10 (depends on 7)

The transistor arrangement according to claim 7, wherein a distance from the base to the second opening is smaller than the distance from the base to the first opening.

### Claim 11 (depends on 7)

The transistor arrangement according to claim 7, wherein:
the second opening is lined with a dielectric liner,
the one or more electrically conductive materials at least partially fill the second opening lined with the dielectric liner, and
the dielectric liner includes at least one of the one or more dielectric materials that at least partially fill the first opening.

### Claim 12 (depends on 7)

The transistor arrangement according to claim 7, wherein:
the one or more electrically conductive materials at least partially fill a first portion of the second opening,
the second opening further includes a second portion, at least partially filled with one or more dielectric materials, and
the second portion is closer to the base than the first portion.

### Claim 13 (depends on 7)

The transistor arrangement according to claim 7, further comprising a structure of one or more electrically conductive material, the structure configured to provide electrical coupling between the one or more electrically conductive materials in the second opening and at least one transistor terminal of a transistor in one of the first fin, the second fin, or the third fin.

### Claim 14 (depends on 13)

The transistor arrangement according to claim 13, wherein the at least one transistor terminal is a source terminal or a drain terminal.

### Claim 15

A transistor arrangement, comprising:
a fin, extending away from a base, the fin including one or more semiconductor materials that form a channel region of a transistor;
one or more dielectric materials surrounding a first portion of the fin;
one or more gate electrode materials, surrounding and enclosing a second portion of the fin, where the first portion is closer to the base than the second portion, and the second portion includes an edge of the fin that is opposite the base; and
an opening extending through the one or more gate electrode materials and into the one or more dielectric materials surrounding the first portion of the fin, the opening at least partially filled with one or more electrically conductive materials, the one or more electrically conductive materials configured to provide power or signals to at least one terminal of the transistor.

### Claim 16 (depends on 15)

The transistor arrangement according to claim 15, wherein:
the one or more gate electrode materials are shaped as a ridge, substantially perpendicular to the length of the fin and enclosing the second portion of the fin,
the ridge is one of a plurality of ridges of the one or more gate electrode materials, each of the plurality of ridges provided over a different area of the second portion of the fin, and
the opening extends through two or more of the plurality of ridges.

### Claim 17 (depends on 15)

The transistor arrangement according to claim 15, wherein:
the opening includes a liner of one or more dielectric materials at a bottom and inner sidewalls of the opening, and
the one or more electrically conductive materials fill the opening lined with the liner.

### Claim 18 (depends on 15)

The transistor arrangement according to claim 15, wherein:
the one or more electrically conductive materials at least partially fill a first portion of the opening,
the opening further includes a second portion, at least partially filled with one or more dielectric materials, and
the second portion is closer to the base than the first portion.

### Claim 19

A method of forming a transistor arrangement, the method comprising:
providing a fin of one or more semiconductor materials, the fin extending away from a base;
providing a layer of one or more dielectric materials surrounding lower portions of the fin;
providing a ridge of one or more gate electrode materials surrounding and enclosing a second portion of the fin, where the first portion is closer to the base than the second portion, and the second portion includes an edge of the fin that is opposite the base;
performing an etch to form, substantially simultaneously, a first opening and a second opening, where:
the first opening extends through a first portion of the ridge and into a first portion of the layer of one or more dielectric materials by a first distance,
the second opening extends through a second portion of the ridge and into a second portion of the layer of one or more dielectric materials by a second distance,
a width of the first opening is smaller than a width of the second opening, and
the first distance is smaller than the second distance;
depositing one or more dielectric materials into the first opening and the second opening; and
depositing one or more electrically conductive into the second opening after the one or more dielectric materials have been deposited into the second opening.

### Claim 20 (depends on 19)

The method according to claim 19, wherein:
the one or more dielectric materials substantially fill the first opening,
the one or more dielectric materials form a liner in the second opening, and
the one or more electrically conductive materials are deposited into the second opening wherein the one or more dielectric materials separate the one or more electrically conductive materials from the one or more gate electrode materials.