# US 2021/0280703 A1 · Charge-trapping layers for iii-v semiconductor devices

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- Number: US 2021/0280703 A1
- Document ID: US20210280703A1
- Status: Published application
- Kind: A1
- Application number: 16/807,623
- Filed: 2020-03-03
- Published: 2021-09-09
- Earliest claimed: 2020-03-03
- Assignees: GlobalFoundries U.S. Inc.
- Applicants: GLOBALFOUNDRIES U.S. Inc.
- Inventors: Bartlomiej J. Pawlak; Dimitri Lederer
- Web page: https://patentgrep.com/patent/US20210280703A1

## CPC

- H10D 30/4738: {having multiple donor layers}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 62/357: {of FETs}
- H10D 62/8171: {Doping structures, e.g. doping superlattices or nipi superlattices}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/834: further characterised by the dopants
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10P 14/3216: {Nitrides}
- H10P 14/3252: {Alternating layers, e.g. superlattice}
- H10P 14/3416: {Nitrides}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Structures including a buffer layer and methods of forming a structure including a buffer layer. A layer stack is formed on a semiconductor substrate. The layer stack includes a buffer layer and a charge-trapping layer. The buffer layer is composed of a III-V compound semiconductor material, and the charge-trapping layer is positioned between the semiconductor substrate and the buffer layer.

## Claims

### Claim 1

A structure comprising:
a semiconductor substrate; and
a layer stack on the semiconductor substrate, the layer stack including a buffer layer and a first charge-trapping layer, the buffer layer comprised of a III-V compound semiconductor material, and the first charge-trapping layer positioned between the semiconductor substrate and the buffer layer.

### Claim 2 (depends on 1)

The structure of claim 1 wherein the first charge-trapping layer is comprised of a single-crystal semiconductor material containing an atomic concentration of an element that provides charge traps in the single-crystal semiconductor material.

### Claim 3 (depends on 1)

The structure of claim 1 wherein the first charge-trapping layer is comprised of single-crystal silicon containing an atomic concentration of an element from Group IV of the Periodic Table.

### Claim 4 (depends on 1)

The structure of claim 1 wherein the first charge-trapping layer is comprised of single-crystal silicon containing an atomic concentration of carbon.

### Claim 5 (depends on 4)

The structure of claim 4 wherein the atomic concentration of carbon in the single-crystal silicon is within a range of about 0.1 atomic percent to about 3 atomic percent.

### Claim 6 (depends on 1)

The structure of claim 1 wherein the first charge-trapping layer is comprised of single-crystal silicon and contains an atomic concentration of a non-doping element in the single-crystal silicon.

### Claim 7 (depends on 1)

The structure of claim 1 wherein the layer stack further includes a first cap layer positioned between the first charge-trapping layer and the buffer layer.

### Claim 8 (depends on 7)

The structure of claim 7 wherein the first cap layer and the first charge-trapping layer are comprised of a single-crystal semiconductor material, the single-crystal semiconductor material of the first charge-trapping layer contains an atomic concentration of carbon, and the first cap layer is free of carbon.

### Claim 9 (depends on 7)

The structure of claim 7 wherein the layer stack further includes a second charge-trapping layer, and the first cap layer is positioned between the first charge-trapping layer and the second charge-trapping layer.

### Claim 10 (depends on 9)

The structure of claim 9 wherein the layer stack further includes a second cap layer, and the second charge-trapping layer is positioned between the first cap layer and the second cap layer.

### Claim 11 (depends on 9)

The structure of claim 9 wherein the first charge-trapping layer and the second charge-trapping layer are comprised of a single-crystal semiconductor material containing an atomic concentration of an element that provides charge traps in the single-crystal semiconductor material.

### Claim 12 (depends on 9)

The structure of claim 9 wherein the first charge-trapping layer and the second charge-trapping layer are comprised of single-crystal silicon containing an atomic concentration of an element from Group IV of the Periodic Table.

### Claim 13 (depends on 9)

The structure of claim 9 wherein the first charge-trapping layer and the second charge-trapping layer are comprised of single-crystal silicon containing an atomic concentration of carbon.

### Claim 14 (depends on 13)

The structure of claim 13 wherein the atomic concentration of carbon in the single-crystal silicon is within a range of about 0.1 atomic percent to about 3 atomic percent.

### Claim 15 (depends on 9)

The structure of claim 9 wherein the first charge-trapping layer and the second charge-trapping layer are comprised of single-crystal silicon and contain an atomic concentration of a non-doping element in the single-crystal silicon.

### Claim 16 (depends on 1)

The structure of claim 1 further comprising:
a channel layer positioned over the layer stack, the channel layer comprised of a single-crystal III-V compound semiconductor material.

### Claim 17 (depends on 16)

The structure of claim 16 further comprising:
a high-electron-mobility transistor having a gate over the channel layer.

### Claim 18

A method comprising:
forming a charge-trapping layer on a semiconductor substrate; and
forming a buffer layer on the charge-trapping layer,
wherein the buffer layer is comprised of a III-V compound semiconductor material, and the charge-trapping layer is positioned between the semiconductor substrate and the buffer layer.

### Claim 19 (depends on 18)

The method of claim 18 wherein forming the charge-trapping layer on the semiconductor substrate comprises:
epitaxially growing the charge-trapping layer on the semiconductor substrate.

### Claim 20 (depends on 18)

The method of claim 18 wherein the charge-trapping layer is comprised of single-crystal silicon containing an atomic concentration of carbon, and the atomic concentration of carbon in the single-crystal silicon is within a range of about 0.1 atomic percent to about three (3) atomic percent.