# US 2021/0280702 A1 · GALLIUM NITRIDE (GaN) BASED TRANSISTOR WITH MULTIPLE p-GaN BLOCKS

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- Number: US 2021/0280702 A1
- Document ID: US20210280702A1
- Status: Published application
- Kind: A1
- Application number: 17/330,012
- Filed: 2021-05-25
- Published: 2021-09-09
- Earliest claimed: 2019-03-06
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Chang Soo SUH; Sameer Prakash PENDHARKAR; Naveen TIPIRNENI; Jungwoo JOH
- Web page: https://patentgrep.com/patent/US20210280702A1

## CPC

- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/311: {Gate electrodes for field-effect devices}
- H10P 14/3416: {Nitrides}
- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10D 62/343: {Gate regions of field-effect devices having PN junction gates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

In some examples, a gallium nitride (GaN)-based transistor, comprises a substrate; a GaN layer supported by the substrate; an aluminum nitride gallium (AlGaN) layer supported by the GaN layer; a p-doped GaN structure supported by the AlGaN layer; and multiple p-doped GaN blocks supported by the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.

## Claims

### Claim 1

A method, comprising:
obtaining a substrate including a heterostructure;
depositing a p-type gallium nitride (GaN) layer on the heterostructure; and
selectively etching the p-type gallium nitride (GaN) layer to form a p-type GaN structure in a gate area of a GaN transistor and multiple p-type GaN blocks in a drain area of the GaN transistor.

### Claim 2 (depends on 1)

The method of claim 1 further comprising depositing gate, source, first drain contact structures, and blocks of a second drain contact structure, wherein the gate contact structure is supported by the p-type GaN structure, the source contact structure is supported by the heterostructure, the first drain contact structure is supported by the heterostructure, and the blocks of the second drain contact structure are supported by the multiple p-type GaN blocks.

### Claim 3 (depends on 1)

The method of claim 1, wherein the heterostructure comprises a GaN layer and an AlGaN layer disposed on the GaN layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein a first contour of a two-dimensional electron gas (2DEG) of the GaN transistor has a first depletion region, wherein a second contour of the 2DEG has second and third depletion regions.

### Claim 5

A method of forming a gallium nitride (GaN)-based transistor, comprising:
forming a GaN layer on a substrate;
forming an aluminum nitride gallium (AlGaN) layer over the GaN layer;
forming a p-doped GaN structure over the AlGaN layer;
forming a source contact structure over the AlGaN layer;
forming a first drain contact structure over the AlGaN layer; and
forming multiple p-doped GaN blocks over the AlGaN layer and located between the p-doped GaN structure and the first drain contact structure, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks,
wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.

### Claim 6 (depends on 5)

The method of claim 5 further comprising:
forming multiple second drain contact structures located between the p-doped GaN structure and the first drain contact structure, each of the multiple second drain contact structures physically separated from the remaining second drain contact structures, and each of the multiple second drain contact structures disposed on a different one of the multiple p-doped GaN blocks, wherein each of the multiple second drain contact structures electrically couples to the first drain contact structure; and
forming a gate contact structure on the p-doped GaN structure.

### Claim 7 (depends on 6)

The method of claim 6, wherein the second contour of the 2DEG has first and second depletion regions, wherein the first depletion region is positioned below the p-doped GaN structure, and wherein the second depletion region is positioned below one of the multiple p-doped GaN blocks.

### Claim 8

A method of forming a transistor, comprising:
forming a GaN layer supported over a substrate;
forming an aluminum nitride gallium (AlGaN) layer over the GaN layer;
forming a p-doped GaN structure over the AlGaN layer;
forming a source contact structure over the AlGaN layer;
forming a drain contact structure over the multiple p-doped GaN blocks;
forming a gate contact structure over the p-doped GaN structure; and
forming multiple p-doped GaN blocks supported over the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein a linear portion of the drain contact structure overlies the multiple p-doped GaN blocks,
wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.

### Claim 9 (depends on 8)

The method of claim 8, wherein the second contour of the 2DEG has a first depletion region below the drain contact structure and a second depletion region below the gate contact structure.

### Claim 10 (depends on 9)

The method of claim 9, wherein the first contour of the 2DEG has a single depletion region, wherein the second contour of 2DEG has two depletion regions.

### Claim 11 (depends on 8)

The method of claim 8, wherein a first consecutive pair of the multiple p-doped GaN blocks is at a first distance from each other and a second consecutive pair of the multiple p-doped GaN blocks is at a second distance from each other.

### Claim 12 (depends on 11)

The method of claim 11, wherein the first and second distances are equal.

### Claim 13 (depends on 9)

The method of claim 9, wherein one of the multiple p-doped GaN blocks has a first thickness and a first length, wherein another one of the multiple p-doped GaN blocks has a second thickness and a second length.

### Claim 14 (depends on 13)

The method of claim 13, wherein the first length equals the second length, and the first thickness equals the second thickness.

### Claim 15

A method, comprising:
forming a GaN layer over a substrate;
forming an aluminum nitride gallium (AlGaN) layer over the AlGaN layer;
forming a p-doped GaN layer over the AlGaN layer;
forming a gate contact structure on the p-doped GaN layer;
forming a first drain contact structure on the AlGaN layer;
forming multiple p-doped GaN blocks over the AlGaN layer, wherein the multiple p-doped GaN blocks are located between the p-doped GaN layer and a same linear portion of the first drain contact structure;
forming multiple second drain contact structures, each of the multiple second drain contact structures physically separated from the remaining second drain contact structures, and each of the multiple second drain contact structures is disposed on a different one of the multiple p-doped GaN blocks, wherein each of the multiple second drain contact structures conductively couples to the first drain contact structure; and
forming a source contact structure disposed on the AlGaN layer.

### Claim 16 (depends on 11)

The method of claim 11, wherein the AlGaN layer has a chemical composition of Al(X)In(Y)Ga(1−X−Y)N, wherein X and Y are nonzero concentrations of aluminum and indium, respectively.

### Claim 17 (depends on 15)

The method of claim 15, wherein a first contour of a two-dimensional electron gas (2DEG) of the GaN-based transistor is present below the p-doped GaN structure, and wherein a second contour of the 2DEG is present below the first p-doped GaN structure and at least one of the multiple p-doped GaN blocks.

### Claim 18 (depends on 15)

The method of claim 15, wherein a first contour of the 2DEG has a first depletion region, wherein a second contour of the 2DEG has second and third depletion regions.

### Claim 19 (depends on 15)

The method of claim 15, wherein a first consecutive pair of the multiple p-doped GaN blocks is at a first distance from each other and a second consecutive pair of the multiple p-doped GaN blocks is at a second different distance from each other.

### Claim 20 (depends on 15)

The method of claim 15, wherein a first consecutive pair of the multiple p-doped GaN blocks is at a distance from each other and a second consecutive pair of the multiple p-doped GaN blocks is at a same distance from each other.