# US 2021/0280700 A1 · A Vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a Method of Forming the Same

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- Number: US 2021/0280700 A1
- Document ID: US20210280700A1
- Status: Published application
- Kind: A1
- Application number: 16/611,888
- Filed: 2018-05-08
- Published: 2021-09-09
- Earliest claimed: 2017-05-12
- Assignees: C2Amps AB
- Applicants: C2Amps AB
- Inventors: Lars-Erik Wernersson; Olli-Pekka Kilpi
- Web page: https://patentgrep.com/patent/US20210280700A1

## CPC

- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 64/01: Manufacture or treatment
- H10D 64/111: {Field plates}
- H10D 64/205: {Nanosized electrodes, e.g. nanowire electrodes}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10P 14/279: {Vapour-liquid-solid growth}
- H10P 14/3421: {Arsenides}
- H10P 14/3462: {Nanowires}
- H10W 10/051: {of isolation region based on field-effect}
- H10W 10/50: Isolation regions based on field-effect
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A vertical metal oxide semiconductor field effect transistor (MOSFET) and a method for forming a vertical MOSFET is presented. The MOSFET comprises: a top contact; a bottom contact; a nanowire (602) forming a charge transport channel between the top contact and the bottom contact; and a wrap-around gate (650) enclosing the nanowire (602) circumference, the wrap-around gate (650) having an extension spanning over a portion of the nanowire (602) in a longitudinal direction of the nanowire (602), wherein the wrap-around gate (650) comprises a gate portion (614) and a field plate portion (616) for controlling a charge transport in the charge transport channel, and wherein the field plate portion (616) is arranged at a first radial distance (636) from the center of the nanowire (602) and the gate portion (614) is arranged at a second radial distance (634) from the center of the nanowire (602); characterized in that the first radial distance (636) is larger than the second radial distance (634).

## Claims

### Claim 1

A vertical metal oxide semiconductor field effect transistor (MOSFET) comprising:
a top contact;
a bottom contact;
a nanowire forming a charge transport channel between the top contact and the bottom contact; and
a wrap-around gate enclosing the nanowire circumference, the wrap-around gate having an extension spanning over a portion of the nanowire in a longitudinal direction of the nanowire, wherein the wrap-around gate comprises a gate portion and a field plate portion for controlling a charge transport in the charge transport channel, and wherein the field plate portion is arranged at a first radial distance from the center of the nanowire and the gate portion is arranged at a second radial distance from the center of the nanowire;
characterized in that the first radial distance (636) is larger than the second radial distance.

### Claim 2 (depends on 1)

The vertical MOSFET according to claim 1, wherein a material composition of the nanowire varies along the longitudinal direction of the nanowire.

### Claim 3 (depends on 2)

The vertical MOSFET according to claim 2, wherein the material composition of the nanowire along the longitudinal direction of the nanowire is varied gradually.

### Claim 4 (depends on 2)

The vertical MOSFET according to claim 2, wherein the material composition of the nanowire along the longitudinal direction of the nanowire is segmented.

### Claim 5 (depends on 2)

The vertical MOSFET according to claim 2, wherein the material composition of the nanowire varies such that a bandgap of the nanowire is larger adjacent to the field plate portion than adjacent to the gate portion.

### Claim 6 (depends on 1)

The vertical MOSFET according to claim 1, wherein a material composition of the nanowire comprises InxGa1-xAs.

### Claim 7 (depends on 1)

The vertical MOSFET according to claim 1, wherein the wrap-around gate comprises a high-k dielectric.

### Claim 8 (depends on 1)

The vertical MOSFET according to claim 1, wherein a radial extension of the nanowire is smaller at the gate portion than at the field plate portion.

### Claim 9 (depends on 1)

The vertical MOSFET according to claim 1, wherein the nanowire has a radial extension in a range of 2.5 nm to 25 nm.

### Claim 10 (depends on 1)

The vertical MOSFET according to claim 1, wherein the gate portion has an extension in the longitudinal direction of the nanowire in a range of 10 nm to 500 nm, and wherein the field plate portion has an extension in the longitudinal direction of the nanowire in a range of 10 nm to 1000 nm.

### Claim 11 (depends on 1)

The vertical MOSFET according to claim 1, wherein a ratio between the first radial distance and the second radial distance (634) is in a range of 1.1 to 5.

### Claim 12

A method for forming a vertical metal oxide semiconductor field effect transistor (MOSFET) on a substrate having a vertical nanowire arranged on a first major surface of the substrate, the method comprising:
forming a dielectric layer covering outer surfaces of the nanowire and a portion of the first major surface of the substrate adjacent to the nanowire;
forming a first horizontal sacrificial layer covering the dielectric layer around a bottom portion of the nanowire;
removing exposed portions of the dielectric layer using the first sacrificial layer as an etch mask;
removing the first sacrificial layer;
forming a gate stack layer covering remaining portions of the dielectric layer and exposed portions of the nanowire, wherein the gate stack layer comprises a high-k dielectric;
depositing a metal layer covering the gate stack layer;
forming a second horizontal sacrificial layer covering the metal layer around a bottom portion of the nanowire;
removing exposed portions of the metal layer using the second sacrificial layer as an etch mask;
removing exposed portions of the gate stack layer using the second sacrificial layer as an etch mask;
removing the second sacrificial layer, thereby exposing a wrap-around gate enclosing the nanowire circumference, the wrap-around gate being formed of remaining portions of the gate stack layer and the metal layer; and
forming a top contact at a top portion of the nanowire.

### Claim 13 (depends on 12)

The method according to claim 12, the method further comprising:
forming a coating on an upper portion of the nanowire prior to forming the dielectric layer.

### Claim 14 (depends on 13)

The method according to claim 13, the method further comprising:
etching the nanowire, subsequent to removing the first sacrificial layer and prior to forming the gate stack layer, using the coating and/or the dielectric layer as an etch mask, thereby locally decreasing a radial extent of the nanowire.

### Claim 15 (depends on 11)

The method according to claim 11, wherein an upper surface of the second sacrificial layer defines a height of the wrap-around gate.