# US 2021/0280698 A1 · Thyristor, triac and transient-voltage-suppression diode manufacturing

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- Number: US 2021/0280698 A1
- Document ID: US20210280698A1
- Status: Published application
- Kind: A1
- Application number: 17/188,826
- Filed: 2021-03-01
- Published: 2021-09-09
- Earliest claimed: 2020-03-05
- Assignees: STMicroelectronics (Tours) SAS
- Applicants: STMicroelectronics (Tours) SAS
- Inventors: Patrick HAUTTECOEUR; Vincent CARO
- Web page: https://patentgrep.com/patent/US20210280698A1

## CPC

- H10D 18/00: Thyristors
- H10D 18/80: Bidirectional devices, e.g. triacs
- H10D 18/01: Manufacture or treatment
- H10D 18/021: {of bidirectional devices, e.g. triacs}
- H10D 62/104: {having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10W 74/134: {the encapsulations being in grooves in the semiconductor body}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 74/147: {the encapsulations being multilayered}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A device includes a semiconductor substrate. A step is formed at a periphery of the semiconductor substrate. A first layer, made of polysilicon doped in oxygen, is deposited on top of and in contact with a first surface of the substrate. This first layer extends at least on a wall and bottom of the step. A second layer, made of glass, is deposited on top of the first layer and the edges of the first layer. The second layer forms a boss between the step and a central area of the device.

## Claims

### Claim 1

A device, comprising:
a semiconductor substrate including a step at a periphery of the semiconductor substrate;
a first layer on top of and in contact with a first surface of the semiconductor substrate and extending at least on and in contact with a wall and bottom of said step, wherein the first layer is made of polysilicon doped with oxygen; and
a second layer extending on and in contact with the first layer and on edges of the first layer, said second layer forming a boss between the step and a central area of the device, wherein the second layer is made of glass.

### Claim 2 (depends on 1)

The device of claim 1, wherein the second layer comprises a first glass sub-layer on and in contact with the first layer and aligned therewith and a second glass sub-layer extending on and in contact with the first glass sub-layer and covering edges of the first layer and the first glass sub-layer.

### Claim 3 (depends on 2)

The device of claim 2, wherein the first sub-layer has a thickness, at the level of the boss, in a range from 5 μm to 30 μm.

### Claim 4 (depends on 2)

The device of claim 2, wherein the first sub-layer has a thickness, at the level of the boss, in a range from 10 μm to 20 μm.

### Claim 5 (depends on 2)

The device of claim 2, wherein the first sub-layer has a thickness, at the level of the boss, equal to approximately 13 μm.

### Claim 6 (depends on 2)

The device of claim 2, wherein the first sub-layer has a thickness, at the bottom of the step, in a range from 20 μm to 60 μm.

### Claim 7 (depends on 2)

The device of claim 2, wherein the first sub-layer has a thickness, at the bottom of the step, in a range from 30 μm to 40 μm.

### Claim 8 (depends on 2)

The device of claim 2, wherein the first sub-layer has a thickness, at the bottom of the step, equal to approximately 35 μm.

### Claim 9 (depends on 2)

The device of claim 2, wherein the second sub-layer has a thickness in a range from 5 μm to 20 μm.

### Claim 10 (depends on 2)

The device of claim 2, wherein the second sub-layer has a thickness equal to approximately 13 μm.

### Claim 11 (depends on 1)

The device of claim 1, wherein the first layer has a thickness in a range from 0.2 μm to 1 μm.

### Claim 12 (depends on 1)

The device of claim 1, wherein the first layer has a thickness equal to approximately 0.5 μm.

### Claim 13 (depends on 1)

The device of claim 1, wherein the boss has a thickness in a range from 10 μm to 50 μm.

### Claim 14 (depends on 1)

The device of claim 1, wherein the boss has a thickness in a range from 10 μm to 35 μm.

### Claim 15 (depends on 1)

The device of claim 1, wherein the boss has a thickness equal to approximately 15 μm.

### Claim 16 (depends on 1)

The device of claim 1, wherein the step has a depth in a range from 80 μm to 200 μm.

### Claim 17 (depends on 1)

The device of claim 1, wherein the step has a depth equal to approximately 105 μm.

### Claim 18

An electronic component comprising the step, first layer and second layer on each surface of the semiconductor substrate to form circuit component selected from the group consisting of: a thyristor, a triac and a transient-voltage-suppression diode.

### Claim 19

A method of manufacturing a device, comprising:
forming a step at a periphery of a semiconductor substrate;
forming a first layer on top of and in contact with a first surface of the semiconductor substrate, the first layer extending at least on and in contact with walls and bottoms of said step, wherein the first layer is made of polysilicon doped with oxygen; and
forming a second layer extending on and in contact with the first layer and the edges of the first layer to form, between the step and a central portion of the device, a boss, wherein the second layer is made of glass.

### Claim 20 (depends on 19)

The method of claim 19, wherein the forming of the second layer comprises:
forming a first glass sub-layer on and in contact with the first layer;
first wet etching of the first layer and the first glass sub-layer along a pattern of a first mask formed by photolithography;
forming a second glass sub-layer on and in contact with the first glass sub-layer so that the second glass sub-layer covers the first glass sub-layer and edges of the first layer and the first glass sub-layer, to form the boss at an inner periphery of the step; and
second wet etching of the second sub-layer along a pattern of a second mask formed by photolithography.

### Claim 21 (depends on 20)

The method of claim 20, wherein the first wet etching is carried out in a bath, made of approximately 59% of ammonium fluoride, approximately 6% of hydrogen fluoride, and approximately 35% of hydrogen peroxide.

### Claim 22 (depends on 20)

The method of claim 20, wherein the second wet etching is carried out in a bath, made of approximately 50% of hydrogen fluoride, and approximately 50% of hydrochloric acid.

### Claim 23 (depends on 20)

The method of claim 20, wherein the first and second wet etchings are carried out in baths having a temperature in a range from eighteen degrees Celsius to thirty degrees Celsius.

### Claim 24 (depends on 20)

The method of claim 20, wherein the first and second wet etchings are carried out in baths having a temperature in a range from twenty degrees Celsius to twenty-five degrees Celsius.

### Claim 25 (depends on 20)

The method of claim 20, wherein the first and second wet etchings are carried out in baths having a temperature equal to approximately twenty-two degrees Celsius.

### Claim 26 (depends on 20)

The method of claim 20, wherein the first etching has a duration in a range from thirty minutes to sixty minutes.

### Claim 27 (depends on 20)

The method of claim 20, wherein the first etching has a duration in a range from forty minutes to fifty minutes.

### Claim 28 (depends on 20)

The method of claim 20, wherein the second etching has a duration in a range from one minute to two minutes.

### Claim 29 (depends on 20)

The method of claim 20, wherein the second etching has a duration in a range from one minute and fifteen seconds to one minute and forty seconds.

### Claim 30 (depends on 19)

The method of claim 19, wherein the first layer is deposited by low-pressure chemical vapor deposition.

### Claim 31 (depends on 19)

The method of claim 19, wherein the first layer is deposited by plasma enhanced chemical vapor deposition.