# US 2021/0280696 A1 · Epitaxial Structures for Fin-Like Field Effect Transistors

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- Number: US 2021/0280696 A1
- Document ID: US20210280696A1
- Status: Published application
- Kind: A1
- Application number: 17/324,512
- Filed: 2021-05-19
- Published: 2021-09-09
- Earliest claimed: 2017-11-10
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chia-Ta Yu; Sheng-Chen Wang; Feng-Cheng Yang; Yen-Ming Chen; Sai-Hooi Yeong
- Web page: https://patentgrep.com/patent/US20210280696A1

## CPC

- H10D 30/0241: {doping of vertical sidewalls, e.g. using tilted or multi-angled implants}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/215: {comprising FinFETs}
- H10P 14/27: {using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 86/011: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes a first fin and a second fin protruding from a substrate, isolation features over the substrate to separate the first and the second fins, where a top surface of each of the first and the second fins is below a top surface of the isolation features, inner fin spacers disposed along inner sidewalls of the first and the second fins, where the inner fin spacers have a first height measured from a top surface of the isolation features, outer fin spacers disposed along outer sidewalls of the first and the second fins, where the outer fin spacers have a second height measured from the top surface of the isolation features that is less than the first height, and a source/drain (S/D) structure merging the first and the second fins, where the S/D structure includes an air gap having a top portion over the inner fin spacers.

## Claims

### Claim 1

A semiconductor structure, comprising:
a first fin and a second fin protruding from a semiconductor substrate;
isolation features disposed over the semiconductor substrate to separate the first and the second fins, wherein a top surface of each of the first and the second fins is below a top surface of the isolation features;
inner fin spacers disposed along inner sidewalls of the first and the second fins, wherein the inner fin spacers have a first height measured from a top surface of the isolation features;
outer fin spacers disposed along outer sidewalls of the first and the second fins, wherein the outer fin spacers have a second height measured from the top surface of the isolation features that is less than the first height; and
a source/drain (S/D) structure merging the first and the second fins, wherein the S/D structure includes an air gap having a top portion disposed over the inner fin spacers.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein a bottom portion of the air gap is disposed between the inner fin spacers.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein the top portion of the air gap is defined by a third height and the bottom portion of the air gap is defined by a fourth height, and wherein the third height is about ⅓ to about ½ of the fourth height.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the S/D structure includes a plurality of facets, wherein the facet directly above the air gap is substantially parallel to the top surfaces of the first and the second fins.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein a height of the air gap measured from the top surface of the isolation features is less than the height of the first and the second fins measured from the top surface of the isolation features.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, wherein the height of the air gap is about 30% to about 80% of the height of the first and the second fins.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the S/D structure includes a first epitaxial layer, a second epitaxial layer over the first epitaxial layer, and a third epitaxial layer over the second epitaxial layer, wherein the first, the second, and the third epitaxial layers include different dopant concentrations.

### Claim 8

A semiconductor structure, comprising:
a first fin and a second fin protruding from a semiconductor substrate;
isolation features disposed over the semiconductor substrate to separate the first and the second fins, wherein a top surface of each of the first and the second fins is below a top surface of the isolation features;
inner fin spacers disposed along inner sidewalls of the first and the second fins;
outer fin spacers formed along outer sidewalls of the first and the second fins, wherein the outer fin spacers have a height less than that of the inner fin spacers;
a source/drain (S/D) structure disposed over the first and the second fins, wherein a top portion of the S/D structure that laterally spans from the first fin to the second fin is substantially parallel to top surfaces of the first fin and the second fin; and
an air gap disposed in the S/D structure, wherein the air gap includes a top portion disposed over the inner fin spacers.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, wherein the inner fin spacers have a height measured from the top surface of the isolation features that is greater than half of a height of the first and the second fins measured in a channel region from the top surface of the isolation features.

### Claim 10 (depends on 8)

The semiconductor structure of claim 8, wherein the air gap exposes the top surface of the isolation features.

### Claim 11 (depends on 8)

The semiconductor structure of claim 8, wherein the top portion of the air gap has a first height and a bottom portion of the air gap below the top portion has a second height, and wherein the first height is less than the second height.

### Claim 12 (depends on 11)

The semiconductor structure of claim 11, wherein the first height is about 30% to about 80% of the second height.

### Claim 13 (depends on 8)

The semiconductor structure of claim 8, wherein the S/D structure includes a first epitaxial layer, a second epitaxial layer over the first epitaxial layer, and a third epitaxial layer over the second epitaxial layer, wherein the first, the second, and the third epitaxial layers include different dopant concentrations.

### Claim 14 (depends on 13)

The semiconductor structure of claim 13, wherein a top surface of the first epitaxial layer is above the top surface of each of the first and the second fins.

### Claim 15 (depends on 13)

The semiconductor structure of claim 13, wherein the top portion of the S/D structure is disposed over a top facet of the second epitaxial layer.

### Claim 16

A semiconductor structure, comprising:
a first fin and a second fin protruding from a semiconductor substrate;
isolation features disposed over the semiconductor substrate to separate the first and the second fins, wherein a top surface of each of the first and the second fins is below a top surface of the isolation features;
inner fin spacers disposed along inner sidewalls of the first and the second fins;
outer fin spacers formed along outer sidewalls of the first and the second fins, wherein the outer fin spacers have a height less than that of the inner fin spacers;
an air gap disposed between and protruding over the inner fin spacers; and
a source/drain (S/D) structure disposed over the first and the second fins, wherein the S/D structure includes an epitaxial layer disposed over the inner fin spacers, wherein the epitaxial layer and top surfaces of the inner fin spacers define a top portion of the air gap, and wherein a top portion of the S/D structure that laterally spans from the first fin to the second fin is substantially parallel to top surfaces of the first fin and the second fin.

### Claim 17 (depends on 16)

The semiconductor structure of claim 16, wherein the first and the second fin have a fin height measured in a channel region from the top surface of the isolation features, and wherein the height of the inner fin spacers is at least half of the fin height.

### Claim 18 (depends on 16)

The semiconductor structure of claim 16, wherein the top portion of the air gap has a first height and a bottom portion of the air gap below the top portion has a second height, and wherein the first height is less than the second height.

### Claim 19 (depends on 16)

The semiconductor structure of claim 16, wherein the S/D structure includes a first epitaxial layer, a second epitaxial layer over the first epitaxial layer, and a third epitaxial layer over the second epitaxial layer, wherein the top portion of the S/D structure is disposed over a top facet of the second epitaxial layer.

### Claim 20 (depends on 19)

The semiconductor structure of claim 19, wherein a top surface of the first epitaxial layer is above the top surface of each of the first and the second fins.