# US 2021/0280690 A1 · Using selectively formed cap layers to form self-aligned contacts to source/drain regions

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- Number: US 2021/0280690 A1
- Document ID: US20210280690A1
- Status: Published application
- Kind: A1
- Application number: 16/810,114
- Filed: 2020-03-05
- Published: 2021-09-09
- Earliest claimed: 2020-03-05
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Chanro Park; ChoongHyun Lee; Kangguo Cheng; Ruilong Xie
- Web page: https://patentgrep.com/patent/US20210280690A1

## CPC

- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D 84/834: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10P 14/6308: {of Group IV semiconductors}
- H10D 30/0215: {using self-aligned selective metal deposition simultaneously on gate electrodes and the source regions or drain regions}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10P 14/6322: {Formation by thermal treatments (formation by plasma treatment H10P14/6319)}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for manufacturing a semiconductor device includes forming a plurality of gate structures on a semiconductor fin, and forming a plurality of source/drain regions adjacent the plurality of gate structures. In the method, a germanium oxide layer is formed on the plurality of gate structures and on the plurality of source/drain regions, and portions of the germanium oxide layer on the plurality of source/drain regions are converted into a plurality of dielectric layers. The method also includes removing unconverted portions of the germanium oxide layer from the plurality of gate structures, and depositing a plurality of cap layers in place of the removed unconverted portions of the germanium oxide layer. The plurality of dielectric layers are removed, and a plurality of source/drain contacts are formed on the plurality of source/drain regions. The plurality of source/drain contacts are adjacent the plurality of cap layers.

## Claims

### Claim at position 1

-11. (canceled)

### Claim 12

A semiconductor device, comprising:
a plurality of gate structures disposed on a semiconductor fin;
a plurality of spacers disposed on sides of the plurality of gate structures;
a plurality of cap layers disposed on the plurality of gate structures and on the plurality of spacers;
a plurality of source/drain regions disposed adjacent the plurality of gate structures; and
a plurality of source/drain contacts disposed on the plurality of source/drain regions;
wherein the plurality of source/drain contacts are disposed between the plurality of cap layers and the plurality of gate structures.

### Claim 13 (depends on 12)

The semiconductor device according to claim 12, wherein:
top surfaces of the plurality of gate structures are coplanar with top surfaces of the plurality of spacers; and
the plurality of cap layers contact the top surfaces of the plurality of gate structures and the plurality of spacers.

### Claim 14 (depends on 12)

The semiconductor device according to claim 12, wherein the plurality of cap layers each comprise a stepped portion.

### Claim 15 (depends on 12)

The semiconductor device according to claim 12, wherein:
top surfaces of the plurality of gate structures are recessed with respect to top surfaces of the plurality of spacers; and
the plurality of cap layers contact the top surfaces of the plurality of gate structures and the top surfaces of the plurality of spacers.

### Claim at position 6

-20. (canceled)

### Claim 21 (depends on 14)

The semiconductor device according to claim 14, wherein the stepped portions are respectively positioned on respective ones of the plurality of spacers.

### Claim 22 (depends on 14)

The semiconductor device according to claim 14, wherein portions of the plurality of source/drain contacts are positioned on the stepped portions.

### Claim 23 (depends on 12)

The semiconductor device according to claim 12, wherein respective ones of the plurality of source/drain contacts comprise an upper portion and a lower portion, wherein the upper portion has a greater width than the lower portion.

### Claim 24 (depends on 12)

The semiconductor device according to claim 12, wherein respective ones of the plurality of cap layers comprise lateral edges which are coplanar with lateral edges of respective ones of the plurality of spacers.

### Claim 25 (depends on 24)

The semiconductor device according to claim 24, wherein the plurality of source/drain contacts contact the coplanar lateral edges of the plurality of cap layers and of the plurality of spacers.

### Claim 26 (depends on 12)

The semiconductor device according to claim 12, further comprising a plurality of dielectric layers disposed on the plurality of cap layers.

### Claim 27

A semiconductor device, comprising:
a plurality of gate structures disposed on a channel region;
a plurality of spacers disposed on sides of the plurality of gate structures;
a plurality of cap layers disposed on the plurality of gate structures and on the plurality of spacers;
a plurality of source/drain regions disposed adjacent the plurality of gate structures; and
a plurality of source/drain contacts disposed on the plurality of source/drain regions;
wherein the plurality of source/drain contacts are disposed between the plurality of cap layers and the plurality of gate structures.

### Claim 28 (depends on 27)

The semiconductor device according to claim 27, wherein:
top surfaces of the plurality of gate structures are coplanar with top surfaces of the plurality of spacers; and
the plurality of cap layers contact the top surfaces of the plurality of gate structures and the plurality of spacers.

### Claim 29 (depends on 27)

The semiconductor device according to claim 27, wherein the plurality of cap layers each comprise a stepped portion.

### Claim 30 (depends on 29)

The semiconductor device according to claim 29, wherein the stepped portions are respectively positioned on respective ones of the plurality of spacers.

### Claim 31 (depends on 29)

The semiconductor device according to claim 29, wherein portions of the plurality of source/drain contacts are positioned on the stepped portions.

### Claim 32 (depends on 27)

The semiconductor device according to claim 27, wherein:
top surfaces of the plurality of gate structures are recessed with respect to top surfaces of the plurality of spacers; and
the plurality of cap layers contact the top surfaces of the plurality of gate structures and the top surfaces of the plurality of spacers.

### Claim 33 (depends on 27)

The semiconductor device according to claim 27, wherein respective ones of the plurality of source/drain contacts comprise an upper portion and a lower portion, wherein the upper portion has a greater width than the lower portion.

### Claim 34 (depends on 27)

The semiconductor device according to claim 27, wherein respective ones of the plurality of cap layers comprise lateral edges which are coplanar with lateral edges of respective ones of the plurality of spacers.

### Claim 35 (depends on 34)

The semiconductor device according to claim 34, wherein the plurality of source/drain contacts contact the coplanar lateral edges of the plurality of cap layers and of the plurality of spacers.

### Claim 36 (depends on 27)

The semiconductor device according to claim 27, further comprising a plurality of dielectric layers disposed on the plurality of cap layers.