# US 2021/0280685 A1 · Low noise and high-performance field effect transistors of 2-dimensional materials and methods to fabricate the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0280685 A1 - Document ID: US20210280685A1 - Status: Published application - Kind: A1 - Application number: 17/253,180 - Filed: 2019-06-22 - Published: 2021-09-09 - Earliest claimed: 2018-06-22 - Assignees: Kansas State University Research Foundation; Purdue Research Foundation - Applicants: Kansas State University Research Foundation; Purdue Research Foundation - Inventors: Suprem R. Das; David B. Janes; Jiseok Kwon - Web page: https://patentgrep.com/patent/US20210280685A1 ## CPC - H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium} - H10D 64/605: {Source, drain, or gate electrodes for FETs comprising highly resistive materials} - H10D 30/481: {FETs having two-dimensional material channels, e.g. transition metal dichalcogenide [TMD] FETs} - H10D 48/362: {Unipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions, e.g. hot electron transistors [HET], metal base transistors [MBT], resonant tunnelling transistors [RTT], bulk barrier transistors [BBT], planar doped barrier transistors [PDBT] or charge injection transistors [CHINT]} - H10D 62/80: characterised by the materials - H10D 62/883: {Transition metal dichalcogenides, e.g. MoSe2} - H10D 99/00: Subject matter not provided for in other groups of this subclass - H10P 14/3436: {being chalcogenide semiconductor materials not being oxides, e.g. ternary compounds} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device and methods of fabricating and using the same are provided. The semiconductor device comprises a channel region and at least a first, second, and third electrode. The channel region includes a compound having a transition metal and a chalcogen. The thickness of the channel region is about 3 to about 40 atomic layers. ## Claims ### Claim 1 A semiconductor device comprising: a channel region including a compound having a transition metal and a chalcogen; at least a first and second electrode in contact with the channel region; a resistive layer in contact with the channel region; and a third electrode in contact with the resistive layer, wherein the channel region has a thickness of about 3 to about 40 atomic layers. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the transition metal of the channel region comprises molybdenum. ### Claim 3 (depends on 2) The semiconductor device of claim 2, wherein at least one of the electrodes comprises scandium or nickel. ### Claim 4 (depends on 3) The semiconductor device of claim 3, wherein the chalcogen of the channel region comprises selenium or sulfur. ### Claim 5 (depends on 1) The semiconductor device of claim 1, the channel region having a first surface and a second opposed surface, wherein the first and second electrodes overlie at least a portion of the first surface of the channel region, and the resistive layer is in contact with the second surface of the channel region. ### Claim 6 (depends on 5) The semiconductor device of claim 5, wherein the third electrode comprises doped silicon. ### Claim 7 (depends on 6) The semiconductor device of claim 6, wherein the resistive layer comprises silicon. ### Claim 8 (depends on 7) The semiconductor device of claim 7, wherein the resistive layer comprises silicon dioxide. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein when a biasing voltage of from 50 to 500 mV is applied between the first electrode and the second electrode and a gate voltage is applied between the third electrode and the second electrode an on-current is generated, when the biasing voltage is applied between the first electrode and the second electrode and no gate voltage is applied an off-current is generated, wherein the ratio of the on-current to the off-current is at least 75,000. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein the biasing voltage is about 150 to about 250 mV. ### Claim 11 (depends on 1) The semiconductor device of claim 1, wherein the channel region has a thickness of about 8 to about 20 atomic layers. ### Claim 12 (depends on 1) The semiconductor device of claim 1, wherein the channel region has a thickness that is less than 15 nm. ### Claim 13 (depends on 1) The semiconductor device of claim 1, wherein the semiconductor device is a transistor or a Schottky-barrier field-effect transistor. ### Claim 14 (depends on 1) The semiconductor device of claim 1, wherein the semiconductor device has a Hooge constant that is less than 0.01. ### Claim 15 A semiconductor device comprising: a channel region having a first surface and a second opposed surface and comprising a compound having a transition metal and a chalcogen, the chalcogen comprising a material selected from the group consisting of: selenium and sulfur; a first electrode and a second electrode in contact with the first surface of the channel region; a resistive layer in contact with the second surface of the channel region; a third electrode in contact with the resistive layer; and wherein the channel region has a thickness of about 3 to about 40 atomic layers. ### Claim 16 (depends on 15) The semiconductor device of claim 15, wherein when a biasing voltage of from 50 to 500 mV is applied between the first electrode and the second electrode and a gate voltage is applied between the third electrode and the second electrode an on-current is generated, when the biasing voltage is applied between the first electrode and the second electrode and no gate voltage is applied an off-current is generated, wherein the ratio of the on-current to the off-current is at least 75,000. ### Claim 17 (depends on 16) The semiconductor device of claim 16, wherein the biasing voltage is about 150 to 250 mV. ### Claim 18 (depends on 15) The semiconductor device of claim 15, wherein the semiconductor device has a Hooge constant that is less than 0.01. ### Claim at position 19 19-34. (canceled) ### Claim 35 A method of providing a conductive path, the method comprising: providing a semiconductor device comprising: a channel region having a first surface and a second opposed surface and comprising a compound having a transition metal and a chalcogen, a first electrode and a second electrode in contact with the first surface of the channel region; a resistive layer positioned below the second surface of the channel region, a third electrode in contact with the resistive layer, and wherein the channel region has a thickness of about 8 to about 20 atomic layers; applying a biasing voltage of about 50 to about 500 mV between the first electrode and the second electrode; and applying a gate voltage between the third electrode and the second electrode. ### Claim at position 21 36-41. (canceled) ### Claim 42 (depends on 35) The method of claim 35, wherein the third electrode comprises doped silicon, wherein the resistive layer is in direct contact with the second side of the channel region, and wherein the resistive layer comprises silicon dioxide. ### Claim at position 23 43-61. (canceled)