# US 2021/0280684 A1 · Transistor with insulator

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- Number: US 2021/0280684 A1
- Document ID: US20210280684A1
- Status: Published application
- Kind: A1
- Application number: 16/812,292
- Filed: 2020-03-07
- Published: 2021-09-09
- Earliest claimed: 2020-03-07
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Ye LU; Haining YANG; Junjing BAO
- Web page: https://patentgrep.com/patent/US20210280684A1

## CPC

- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/121: {oriented parallel to substrates}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/026: {having laterally-coplanar source and drain regions, a gate at the sides of the bulk channel, and both horizontal and vertical current flow (of LDMOS H10D30/0289)}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/687: {having cavities, e.g. porous gate dielectrics having gasses therein}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A gate all around transistor may be improved to provide better transistor circuits performance. In one example, a transistor circuit may include a dielectric or air gap as an insulator between the channels of the transistors in the circuit. In another example, a transistor may include a first channel surrounded by a first metal, a second channel surrounded by a second metal proximate to the first channel, and an insulator, such as a dielectric or air gap, between the first metal and the second metal. The insulator helps reduce the parasitic capacitance between the source/drain regions and the metal fill regions of the transistor.

## Claims

### Claim 1

A transistor comprising:
a first channel surrounded by a first metal;
a second channel proximate to and spaced from the first channel, the second channel surrounded by a second metal;
a gate dielectric between the first channel and the first metal and between the second channel and the second metal;
a first insulator between the first metal and the second metal, wherein the first insulator is an air gap enclosed by a dielectric;
a gate on a substrate, the gate encapsulates the first metal, the second metal, and the first insulator;
a source on the substrate proximate the gate; and
a drain on the substrate proximate the gate.

### Claim 2 (depends on 1)

The transistor of claim 1, wherein the transistor is a gate all around field effect transistor.

### Claim 3 (depends on 1)

The transistor of claim 1, wherein the dielectric of the first insulator is at least one of Silicon Carbonitride (SiCN) or Silicon Nitride (SiN).

### Claim 4 (depends on 1)

The transistor of claim 1, wherein the air gap of the first insulator has a cross-section having a horizontal axis that is longer than a vertical axis.

### Claim 5 (depends on 4)

The transistor of claim 4, wherein the cross-section of the air gap has a generally rectangular shape.

### Claim 6 (depends on 1)

The transistor of claim 1, further comprising a third channel proximate and spaced from the second channel opposite the first channel, the third channel surrounded by a third metal.

### Claim 7 (depends on 1)

The transistor of claim 1, wherein the first metal comprises a dielectric material with a dielectric constant greater than 3.9.

### Claim 8 (depends on 1)

The transistor of claim 1, wherein the substrate comprises a shallow trench isolation region.

### Claim 9 (depends on 1)

The transistor of claim 1, wherein the transistor is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle.

### Claim 10

A transistor comprising:
a first channel surrounded by a first metal;
a second channel proximate to and spaced from the first channel, the second channel surrounded by a second metal;
a gate dielectric between the first channel and the first metal and between the second channel and the second metal;
means for insulating between the first metal and the second metal, wherein the means for insulating is an air gap enclosed by a dielectric;
a gate on a substrate, the gate encapsulates the first metal, the second metal, and the means for insulating;
a source on the substrate proximate the gate; and
a drain on the substrate proximate the gate.

### Claim 11 (depends on 10)

The transistor of claim 10, wherein the transistor is a gate all around field effect transistor.

### Claim 12 (depends on 10)

The transistor of claim 10, wherein the dielectric of the means for insulating is at least one of Silicon Carbonitride (SiCN) or Silicon Nitride (SiN).

### Claim 13 (depends on 10)

The transistor of claim 10, wherein the air gap of the means for insulating has a cross-section having a horizontal axis that is longer than a vertical axis.

### Claim 14 (depends on 13)

The transistor of claim 13, wherein the cross-section of the air gap has a generally rectangular shape.

### Claim 15 (depends on 10)

The transistor of claim 10, further comprising a third channel proximate and spaced from the second channel opposite the first channel, the third channel surrounded by a third metal.

### Claim 16 (depends on 10)

The transistor of claim 10, wherein the first metal comprises a dielectric material with a dielectric constant greater than 3.9.

### Claim 17 (depends on 10)

The transistor of claim 10, wherein the substrate comprises a shallow trench isolation region.

### Claim 18 (depends on 10)

The transistor of claim 10, wherein the transistor is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle.

### Claim 19

A method for manufacturing a transistor, the comprising:
providing a substrate;
forming a source on the substrate;
forming a drain on the substrate proximate the source;
forming a first channel surrounded by a first metal proximate the substrate;
forming a second channel proximate to and spaced from the first channel, the second channel surrounded by a second metal;
forming a gate dielectric between the first channel and the first metal and between the second channel and the second metal;
forming a first insulator between the first metal and the second metal, wherein the first insulator is an air gap enclosed by a dielectric; and
forming a gate on the substrate, the gate encapsulates the first metal, the second metal, and the first insulator.

### Claim 20 (depends on 19)

The method of claim 19, wherein the transistor is a gate all around field effect transistor.

### Claim 21 (depends on 19)

The method of claim 19, wherein the dielectric of the first insulator is at least one of Silicon Carbonitride (SiCN) or Silicon Nitride (SiN).

### Claim 22

(canceled)

### Claim 23

(canceled)

### Claim 24 (depends on 19)

The method of claim 19, wherein the method further comprises forming a third channel proximate to and spaced from the second channel opposite the first channel, the third channel surrounded by a third metal.

### Claim 25 (depends on 19)

The method of claim 19, wherein the first metal comprises a dielectric material with a dielectric constant greater than 3.9.

### Claim 26 (depends on 19)

The method of claim 19, wherein the substrate comprises a shallow trench isolation region.

### Claim 27 (depends on 19)

The method of claim 19, wherein the method further comprises incorporating the transistor into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle.

### Claim 28 (depends on 6)

The transistor of claim 6, further comprising:
a second insulator between the second metal and the third metal, wherein the second insulator is a second air gap enclosed by a second dielectric.

### Claim 29 (depends on 15)

The transistor of claim 15, further comprising:
a second means for insulating between the second metal and the third metal, wherein the second means for insulating is a second air gap enclosed by a second dielectric.