# US 2021/0280680 A1 · Metal-oxide-semiconductor field-effect transistor having enhanced high-frequency performance > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0280680 A1 - Document ID: US20210280680A1 - Status: Published application - Kind: A1 - Application number: 17/130,943 - Filed: 2020-12-22 - Published: 2021-09-09 - Earliest claimed: 2020-03-04 - Assignees: Shanghai Bright Power Semiconductor Co., Ltd. - Inventors: Shuming Xu - Web page: https://patentgrep.com/patent/US20210280680A1 ## CPC - H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates} - H10D 64/518: {characterised by their lengths or sectional shapes} - H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes} - H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)} - H10D 30/66: Vertical DMOS [VDMOS] FETs - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 62/10: Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies - H10D 62/157: {Impurity concentrations or distributions} - H10D 62/60: Impurity distributions or concentrations - H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates} - H10D 64/514: {characterised by the insulating layers} - H10D 64/516: {the thicknesses being non-uniform} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A MOSFET device includes an epitaxial region disposed on an upper surface of a substrate, the substrate serving as a drain region in the MOSFET device, and at least two body regions formed in the epitaxial region. The body regions are disposed proximate an upper surface of the epitaxial region and spaced laterally apart. The device further includes at least two source regions disposed in respective body regions, proximate an upper surface of the body regions, and a gate structure including at least two planar gates and a trench gate. Each of the planar gates is disposed on the upper surface of the epitaxial region and overlaps at least a portion of a corresponding body region. The trench gate is formed partially through the epitaxial region and between the body regions. ## Claims ### Claim 1 A metal-oxide semiconductor field-effect transistor (MOSFET) device, comprising: a semiconductor substrate of a first conductivity type, the substrate serving as a drain region in the MOSFET device; an epitaxial region of the first conductivity type disposed on an upper surface of the substrate; a plurality of body regions of a second conductivity type formed in the epitaxial region, the second conductivity type being opposite in polarity to the first conductivity type, the body regions being disposed proximate an upper surface of the epitaxial region and spaced laterally from one another; a plurality of source regions of the first conductivity type, each of the source regions being disposed in a corresponding one of the body regions proximate an upper surface of the body region; and a gate structure comprising a plurality of planar gates and a trench gate, each of the planar gates being disposed on the upper surface of the epitaxial region and overlapping at least a portion of a corresponding body region, the trench gate being formed at least partially through the epitaxial region and between the body regions. ### Claim 2 (depends on 1) The device of claim 1, wherein the at least two planar gates and the trench gate are formed as a contiguous gate having planar gate and trench gate functionality. ### Claim 3 (depends on 2) The device of claim 2, further comprising dielectric spacers formed on respective sidewalls of the at least two planar gates of the gate structure, extending on the upper surface of the epitaxial layer. ### Claim 4 (depends on 1) The device of claim 1, wherein the at least two planar gates and the trench gate are formed as fingered structures that are physically separated from one another, the fingered structures being electrically connected together at one or both ends of the fingered structures. ### Claim 5 (depends on 4) The device of claim 4, further comprising dielectric spacers formed on respective sidewalls of the at least two planar gates of the gate structure and on sidewalls of a portion of the trench gate extending on the upper surface of the epitaxial layer. ### Claim 6 (depends on 1) The device of claim 1, wherein at least one of the trench gate and the at least two planar gates comprises doped polysilicon material. ### Claim 7 (depends on 1) The device of claim 1, wherein the gate structure is configured such that when biased positively above a threshold voltage of an n-channel MOSFET device, a channel is formed in each of the body regions underneath the planar gates, thereby turning on the device, and concurrently a strong accumulation layer of majority carriers is formed in the epitaxial region proximate a surface of the trench gate. ### Claim 8 (depends on 7) The device of claim 7, wherein the gate structure is configured such that a concentration of the majority carriers in the device is modulated as a function of a bias voltage applied to the trench gate. ### Claim 9 (depends on 1) The device of claim 1, further comprising: a first dielectric layer disposed between each of the at least two planar gates and underlying portions of the corresponding body region and epitaxial region; and a second dielectric layer disposed between the trench gate and the adjacent epitaxial region. ### Claim 10 (depends on 9) The device of claim 9, wherein the second dielectric layer is formed having a non-uniform thickness, a first portion of the second dielectric layer, defining a bottom wall of the trench gate and extending partially up sidewalls of the trench gate, having a first thickness associated therewith, and a second portion of the second dielectric layer, extending up the sidewalls of the trench gate and onto the upper surface of the epitaxial layer, having a second thickness associated therewith, the first thickness being greater than the second thickness. ### Claim 11 (depends on 1) The device of claim 1, further comprising at least two doped regions having the second conductivity type formed in the respective body regions proximate the upper surface of the body regions and laterally adjacent to the respective source regions, the two doped regions forming respective body contacts of the device. ### Claim 12 (depends on 1) The device of claim 1, further comprising a plurality of implant regions having the first conductivity type, each of the implant regions being formed in the epitaxial layer, proximate the upper surface of the epitaxial layer, and disposed between a corresponding one of the body regions and the trench gate. ### Claim 13 (depends on 12) The device of claim 12, wherein vertical edges of each of the implant regions are self-aligned with a corresponding one of the planar gates and the trench gate, respectively, of the gate structure. ### Claim 14 (depends on 12) The device of claim 12, wherein a doping concentration of each of the implant regions is about 1×1016 atoms/cm3 to about 1×1018 atoms/cm3. ### Claim 15 (depends on 1) The device of claim 1, wherein a doping concentration of each of the body regions is about 5×1016 atoms/cm3 to about 1×1018 atoms/cm3. ### Claim 16 (depends on 1) The device of claim 1, further comprising a plurality of gate electrodes electrically connected with the respective planar gates and trench gate of the gate structure, each of the gate electrodes comprising a metal silicide layer formed on at least a portion of an upper surface of a corresponding one of the planar gates and trench gate. ### Claim 17 (depends on 1) The device of claim 1, further comprising at least two recessed source contacts, each of the source contacts being formed in a corresponding one of the body regions, proximate an upper surface of the body region, and electrically connected with and adjacent to a corresponding one of the source regions. ### Claim 18 A method of fabricating a metal-oxide semiconductor field-effect transistor (MOSFET) device, the method comprising: forming an epitaxial region of a first conductivity type on an upper surface of a substrate of the first conductivity type, the substrate serving as a drain region in the MOSFET device; forming at least two body regions of a second conductivity type in the epitaxial region, the second conductivity type being opposite in polarity to the first conductivity type, the body regions being disposed proximate an upper surface of the epitaxial region and spaced laterally from one another; forming at least two source regions of the first conductivity type, each of the source regions being disposed in a corresponding one of the body regions proximate an upper surface of the body region; and forming a gate structure comprising at least two planar gates and a trench gate, each of the planar gates being disposed on the upper surface of the epitaxial region and overlapping at least a portion of a corresponding body region, the trench gate being formed at least partially through the epitaxial region between the body regions. ### Claim 19 (depends on 18) The method of claim 18, further comprising forming the at least two planar gates and the trench gate as a contiguous gate having planar gate and trench gate functionality. ### Claim 20 (depends on 18) The method of claim 18, further comprising: forming the at least two planar gates and the trench gate as fingered structures that are physically separated from one another; and electrically connecting the fingered structures together at one or both ends of the fingered structures. ### Claim 21 (depends on 18) The method of claim 18, further comprising: forming a first dielectric layer between each of the at least two planar gates and underlying portions of the corresponding body region and epitaxial region; and forming a second dielectric layer between the trench gate and the adjacent epitaxial region. ### Claim 22 (depends on 21) The method of claim 21, further comprising forming the second dielectric layer having a non-uniform thickness, a first portion of the second dielectric layer, defining a bottom wall of the trench gate and extending partially up sidewalls of the trench gate, having a first thickness associated therewith, and a second portion of the second dielectric layer, extending up the sidewalls of the trench gate and onto the upper surface of the epitaxial layer, having a second thickness associated therewith, the first thickness being greater than the second thickness. ### Claim 23 (depends on 18) The method of claim 18, wherein at least one of the trench gate and the at least two planar gates comprises doped polysilicon material. ### Claim 24 (depends on 18) The method of claim 18, further comprising modulating a concentration of majority carriers in the device as a function of a bias voltage applied to the trench gate. ### Claim 25 (depends on 18) The method of claim 18, further comprising configuring the gate structure whereby when biased above a MOSFET threshold voltage, a channel is formed in each of the body regions underneath the planar gates, thereby turning on the device, and concurrently a strong accumulation layer of majority carriers is formed in the epitaxial region proximate a surface of the trench gate.