# US 2021/0280674 A1 · Field effect transistor structures

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- Number: US 2021/0280674 A1
- Document ID: US20210280674A1
- Status: Published application
- Kind: A1
- Application number: 17/313,700
- Filed: 2021-05-06
- Published: 2021-09-09
- Earliest claimed: 2016-02-17
- Assignees: Tessera, Inc.
- Applicants: Tessera, Inc.
- Inventors: Josephine B. Chang; Bruce B. Doris; Michael A. Guillorn; Isaac Lauer; Xin Miao
- Web page: https://patentgrep.com/patent/US20210280674A1

## CPC

- H10D 62/121: {oriented parallel to substrates}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/01: Manufacture or treatment
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Field effect transistors include a stack of nanowires of vertically arranged channel layers. A source and drain region is disposed at respective ends of the vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Internal spacers are each formed between the gate stack and a respective source or drain region, with at least one pair of spacers being positioned above an uppermost channel layer.

## Claims

### Claim 1

A method of forming a semiconductor device, comprising:
providing sacrificial layers and channel layers over a substrate, wherein the sacrificial layers alternate with channel layers;
etching through the sacrificial layers and the channel layers to form a fin;
forming a plurality of dummy gates over the fin, wherein the plurality of dummy gates comprises at least three dummy gates where two adjacent dummy gates comprise (i) an outside dummy gate over an end of the fin and (ii) a central dummy gate over an interior portion of the fin;
etching through the sacrificial layers and the channel layers using the dummy gates as a mask, wherein the etching leaves a plurality of exposed surfaces of the channel layers and a plurality of exposed surfaces of the sacrificial layers bordering a gap between the outside dummy gate and the central dummy gate; and
epitaxially growing source/drain material on the plurality of exposed surfaces of the channel layers,
wherein source/drain material grown on channel layers merges with source/drain material grown on vertically adjacent channel layers, and
wherein source/drain material grown on channel layers does not merge with source/drain material grown on laterally adjacent channel layers.

### Claim 2 (depends on 1)

The method of claim 1, wherein providing sacrificial layers and channel layers over the substrate comprises depositing alternating layers of sacrificial material and channel material on an insulating layer on the substrate.

### Claim 3 (depends on 2)

The method of claim 2, wherein etching through the sacrificial layers and the channel layers using the dummy gates as a mask etches down to the insulating layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the fin is a nanosheet fin.

### Claim 5 (depends on 1)

The method of claim 1, wherein the fin is a nanowire fin.

### Claim 6 (depends on 1)

The method of claim 1, wherein an uppermost layer of the sacrificial layers and the channel layers is a sacrificial layer.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
subsequent to etching through the sacrificial layers and the channel layers using the dummy gates as a mask, laterally etching the sacrificial layers to form recessed sacrificial layers.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
forming spacers laterally adjacent to the recessed sacrificial layers.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
filling a remaining gap between merged source/drain material on the channel layers of the central dummy gate and merged source/drain material on the channel layers of the outside dummy gate with a dielectric.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
removing the dummy gates;
removing the sacrificial layers;
forming a gate dielectric on the channel layers; and
forming a work function metal on the gate dielectric.

### Claim 11 (depends on 1)

The method of claim 1, further comprising:
subsequent to etching through the sacrificial layers and the channel layers using the dummy gates as a mask, laterally etching the sacrificial layers to form recessed sacrificial layers.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
forming spacers laterally adjacent to the recessed sacrificial layers.

### Claim 13 (depends on 1)

The method of claim 1, wherein epitaxially growing source/drain material on the plurality of exposed surfaces of the channel layers comprises growing source/drain material that follows a crystal structure of the plurality of exposed surfaces of the channel layers.

### Claim 14 (depends on 13)

The method of claim 13, wherein merged source/drain material on the channel layers of the central dummy gate and merged source/drain material on the channel layers of the outside dummy gate each comprise a bottom surface disposed on an insulating layer.

### Claim 15

A method of forming a semiconductor device, the method comprising:
providing sacrificial layers and channel layers over a substrate, wherein the sacrificial layers alternate with channel layers, wherein a lowermost layer is a sacrificial layer, and wherein an uppermost layer is a sacrificial layer;
etching through the sacrificial layers and the channel layers to form a fin;
forming a plurality of dummy gates over the fin, wherein the plurality of dummy gates comprises at least three dummy gates where two adjacent dummy gates comprise (i) an outside dummy gate over an end of the fin and (ii) a central dummy gate over an interior portion of the fin;
etching through the sacrificial layers and the channel layers using the dummy gates as a mask, wherein the etching leaves a plurality of exposed surfaces of the channel layers and a plurality of exposed surfaces of the sacrificial layers bordering a gap between the adjacent outside dummy gate and the central dummy gate;
epitaxially growing source/drain material on the plurality of exposed surfaces of the channel layers, wherein source/drain material grown on channel layers merges with source/drain material grown on vertically adjacent channel layers; and
filling a remaining gap between merged source/drain material on the channel layers of the central dummy gate and merged source/drain material on the channel layers of the outside dummy gate with a dielectric.

### Claim 16 (depends on 15)

The method of claim 15, wherein providing sacrificial layers and channel layers over the substrate comprises depositing alternating layers of sacrificial material and channel material on an insulating layer on the substrate.

### Claim 17 (depends on 15)

The method of claim 15, wherein the fin is a nanosheet fin.

### Claim 18 (depends on 15)

The method of claim 15, wherein the fin is a nanowire fin.

### Claim 19 (depends on 15)

The method of claim 15, wherein an uppermost layer of the sacrificial layers and the channel layers is a sacrificial layer.

### Claim 20 (depends on 15)

The method of claim 15, further comprising:
removing the dummy gates;
removing the sacrificial layers;
forming a gate dielectric on the channel layers; and
forming a work function metal on the gate dielectric.

### Claim 21 (depends on 15)

The method of claim 15, wherein epitaxially growing source/drain material on the plurality of exposed surfaces of the channel layers comprises growing source/drain material that follows a crystal structure of the plurality of exposed surfaces of the channel layers.

### Claim 22 (depends on 21)

The method of claim 21, wherein merged source/drain material on the channel layers of the central dummy gate and merged source/drain material on the channel layers of the outside dummy gate each comprise a bottom surface disposed on an insulating layer.