# US 2021/0280671 A1 · Semiconductor device

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- Number: US 2021/0280671 A1
- Document ID: US20210280671A1
- Status: Published application
- Kind: A1
- Application number: 17/015,640
- Filed: 2020-09-09
- Published: 2021-09-09
- Earliest claimed: 2020-03-04
- Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
- Applicants: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
- Inventors: Kenichi Matsushita
- Web page: https://patentgrep.com/patent/US20210280671A1

## CPC

- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 8/411: {PN diodes having planar bodies}
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/665: {having edge termination structures}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/128: {Anode regions of diodes}
- H10D 64/112: {comprising multiple field plate segments}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 62/8325: {Silicon carbide}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

According to one embodiment, a semiconductor device includes first, second, and third electrodes, first and fourth semiconductor regions of a first conductivity type, and second and third semiconductor regions of a second conductivity type. The third semiconductor region is provided around the second semiconductor region along a first plane crossing a first direction from the first electrode toward the first semiconductor region and is separated from the second semiconductor region. The fourth semiconductor region is provided around the third semiconductor region along the first plane, and has a greater impurity concentration of the first conductivity type than the first semiconductor region. The second electrode is provided on the second semiconductor region and is electrically connected to the second semiconductor region. The third electrode is provided on the third and fourth semiconductor regions, is electrically connected to the third and fourth semiconductor regions, and is separated from the second electrode.

## Claims

### Claim 1

A semiconductor device, comprising:
a first electrode;
a first semiconductor region provided on the first electrode, the first semiconductor region being of a first conductivity type and being electrically connected to the first electrode;
a second semiconductor region provided on the first semiconductor region, the second semiconductor region being of a second conductivity type;
a third semiconductor region provided around the second semiconductor region along a first plane crossing a first direction, the third semiconductor region being of the second conductivity type and being separated from the second semiconductor region, the first direction being from the first electrode toward the first semiconductor region;
a fourth semiconductor region provided around the third semiconductor region along the first plane, the fourth semiconductor region being of the first conductivity type, an impurity concentration of the first conductivity type in the fourth semiconductor region being greater than an impurity concentration of the first conductivity type in the first semiconductor region;
a second electrode provided on the second semiconductor region and electrically connected to the second semiconductor region; and
a third electrode provided on the third and fourth semiconductor regions, electrically connected to the third and fourth semiconductor regions, and separated from the second electrode.

### Claim 2 (depends on 1)

The device according to claim 1, further comprising:
a fifth semiconductor region provided between the second semiconductor region and the third semiconductor region, the fifth semiconductor region being of the first conductivity type,
an impurity concentration of the first conductivity type in the fifth semiconductor region being greater than the impurity concentration of the first conductivity type in the first semiconductor region but less than the impurity concentration of the first conductivity type in the fourth semiconductor region.

### Claim 3 (depends on 2)

The device according to claim 2, further comprising:
a plurality of sixth semiconductor regions provided between the second semiconductor region and the fifth semiconductor region, the plurality of sixth semiconductor regions being of the second conductivity type,
the plurality of sixth semiconductor regions each being provided around the second semiconductor region along the first plane,
the plurality of sixth semiconductor regions being separated from the second and fifth semiconductor regions.

### Claim 4 (depends on 3)

The device according to claim 3, further comprising:
a plurality of conductive layers provided respectively on the plurality of sixth semiconductor regions,
the plurality of conductive layers being electrically connected respectively to the plurality of sixth semiconductor regions,
the plurality of conductive layers each being provided around the second electrode along the first plane.

### Claim 5 (depends on 4)

The device according to claim 4, wherein
one of the plurality of conductive layers is next to the third electrode in a direction from the second electrode toward the third electrode, and
a portion of the one of the plurality of conductive layers and a portion of the third electrode are positioned on the fifth semiconductor region.

### Claim 6 (depends on 2)

The device according to claim 2, wherein
a total impurity amount of the first conductivity type in the fifth semiconductor region is not less than 6.0×1011 atoms/cm2 and not more than 2.0×1012 atoms/cm2.

### Claim 7 (depends on 1)

The device according to claim 1, further comprising:
a seventh semiconductor region provided under the third and fourth semiconductor regions, the seventh semiconductor region being of the first conductivity type,
an impurity concentration of the first conductivity type in the seventh semiconductor region being greater than the impurity concentration of the first conductivity type in the first semiconductor region but less than the impurity concentration of the first conductivity type in the fourth semiconductor region.

### Claim 8 (depends on 1)

The device according to claim 1, further comprising:
an eighth semiconductor region provided on the second semiconductor region, the eighth semiconductor region being of the first conductivity type,
a gate electrode facing the second semiconductor region via a gate insulating layer.

### Claim 9 (depends on 8)

The device according to claim 8, further comprising:
a ninth semiconductor region provided between the first electrode and the first semiconductor region, the ninth semiconductor region being of the second conductivity type.