# US 2021/0280606 A1 · Novel 3d nand memory device and method of forming the same

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- Number: US 2021/0280606 A1
- Document ID: US20210280606A1
- Status: Published application
- Kind: A1
- Application number: 17/330,594
- Filed: 2021-05-26
- Published: 2021-09-09
- Earliest claimed: 2019-06-27
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Jin Yong OH; Youn Cheul KIM
- Web page: https://patentgrep.com/patent/US20210280606A1

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10P 50/73: {using masks for insulating materials}
- H10W 72/0198: {batch processes}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/792: {between multiple chips}
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A 3D-NAND memory includes a transistor formed in a first side of a periphery circuit substrate, a memory cell stack formed over a first side of a cell array substrate, and a first connection structure formed over an opposing second side of the cell array substrate. The memory cell stack includes a doped region formed in the first side of the cell array substrate and coupled to the first connection structure through a first VIA, a common source structure that extends from the doped region toward the first side of the periphery circuit substrate, and a second connection structure that is positioned over and coupled to the common source structure. The first side of the cell array substrate and the first side of the periphery circuit substrate are aligned facing each other so that the transistor is coupled to the second connection structure.

## Claims

### Claim 1

A 3D-NAND memory, comprising:
a transistor formed in a first side of a periphery circuit substrate;
a memory cell stack formed over a first side of a cell array substrate; and
a first connection structure formed over an opposing second side of the cell array substrate,
wherein the memory cell stack includes:
a doped region formed in the first side of the cell array substrate and electrically coupled to at least a source terminal of a memory cell, the doped region being coupled to the first connection structure through a first VIA that extends from the second side of the cell array substrate to the doped region,
a common source structure that extends from the doped region toward the first side of the periphery circuit substrate and is coupled to the doped region, and
a second connection structure that is positioned over and coupled to the common source structure,
wherein the first side of the cell array substrate and the first side of the periphery circuit substrate are aligned facing each other so that the transistor is coupled to the second connection structure.

### Claim 2 (depends on 1)

The 3D-NAND memory of claim 1, further comprising:
a bit line positioned between the common source structure and the second connection structure.

### Claim 3 (depends on 2)

The 3D-NAND memory of claim 2, further comprising:
a second VIA positioned between the common source structure and the bit line; and
a third VIA positioned between the bit line and the second connection structure.

### Claim 4 (depends on 3)

The 3D-NAND memory of claim 3, wherein:
the bit line is coupled to the common source structure through the second VIA, and
the second connection structure is coupled to the bit line through the third VIA.

### Claim 5 (depends on 1)

The 3D-NAND memory of claim 1, wherein the second connection structure is coupled to the transistor through a bonding VIA.

### Claim 6 (depends on 5)

The 3D-NAND memory of claim 5, further comprising a fourth VIA that is arranged between the second connection structure and the bonding VIA and further coupled to the second connection structure, the fourth VIA and the bonding VIA being connected to each other.

### Claim 7 (depends on 1)

The 3D-NAND memory of claim 1, wherein the first VIA further extends through the doped region and contacts the common source structure.

### Claim 8 (depends on 1)

The 3D-NAND memory of claim 1, further comprising:
a spacer layer arranged between the first VIA and the cell array substrate to isolate the first VIA from the cell array substrate.

### Claim 9 (depends on 1)

The 3D-NAND memory of claim 1, further comprising:
a n+ region formed between the first VIA and the doped region, the doped region being n-type.

### Claim 10 (depends on 1)

The 3D-NAND memory of claim 1, wherein the first VIA has at least one of an extended wall-shape that has a tapered cross section or a frustoconical shape.

### Claim 11 (depends on 1)

The 3D-NAND memory of claim 1, wherein the memory cell stack further comprises:
a plurality of word lines stacked over the first side of the cell array substrate, the plurality of word lines including an array region and staircase regions adjacent to the array region; and
a plurality of insulating layers that are disposed between the plurality of word lines, wherein:
the common source structure further extends through the plurality of word lines and the plurality of the insulating layers in the array region.

### Claim 12 (depends on 11)

The 3D-NAND memory of claim 11, further comprising:
a plurality of channel structures extending from the first side of the cell array substrate, the plurality of channel structures extending through the plurality of word lines and the plurality of the insulating layers in the array region; and
a plurality of dummy channel structures extending from the first side of the cell array substrate, the plurality of dummy channel structures extending through the plurality of word lines and the plurality of the insulating layers in the staircase regions.

### Claim 13 (depends on 12)

The 3D-NAND memory of claim 12, wherein the common source structure further extends along a direction parallel to the first side of the cell array substrate to separate the plurality of the channel structures into sub-groups.

### Claim 14 (depends on 12)

The 3D-NAND memory of claim 12, further comprising:
a doped well region formed in the cell array substrate, wherein:
the doped well region extends into the cell array substrate from the first side of the cell array substrate,
the doped well region further extends along the first side of the cell array substrate from a first staircase region of the staircase regions to a second staircase region of the staircase regions, and
the doped region is positioned in the doped well region.

### Claim 15 (depends on 14)

The 3D-NAND memory of claim 14, wherein the doped well region is p-type.

### Claim 16 (depends on 1)

The 3D-NAND memory of claim 1, further comprising:
a through silicon VIA (TSV) that extends from the second side of the cell array substrate to the first side of the cell array substrate so as to be in contact with the second connection structure, wherein the first connection structure is coupled to the second connection structure via the TSV.

### Claim 17 (depends on 1)

The 3D-NAND memory of claim 1, further comprising:
a dielectric layer formed over the second side of the cell array substrate, wherein the first connection structure is formed in the dielectric layer.

### Claim 18 (depends on 3)

The 3D-NAND memory of claim 3, wherein the common source structure further comprises:
a bottom portion that is in contact with the doped region; and
a top portion that is in contact with the second VIA.