# US 2021/0280604 A1 · Three-dimensional vertical nor flash thin-film transistor strings

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- Number: US 2021/0280604 A1
- Document ID: US20210280604A1
- Status: Published application
- Kind: A1
- Application number: 17/328,991
- Filed: 2021-05-24
- Published: 2021-09-09
- Earliest claimed: 2018-02-02
- Assignees: Sunrise Memory Corporation
- Applicants: Sunrise Memory Corporation
- Inventors: Eli Harari; Tianhong Yan
- Web page: https://patentgrep.com/patent/US20210280604A1

## CPC

- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/30: Power supply circuits
- G11C 16/32: Timing circuits
- H10B 43/10: characterised by the top-view layout
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10D 30/6728: {Vertical TFTs}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 64/037: {comprising charge-trapping insulators}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10W 20/4441: {the principal metal being a refractory metal}
- H10W 20/48: Insulating materials thereof
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.

## Claims

### Claim 1

(canceled)

### Claim 2

A thin-film NOR memory string formed above a planar surface of a semiconductor substrate, the semiconductor substrate including circuitry formed therein or thereon for supporting memory circuit operations, comprising:
a common source region and a common drain region each extending lengthwise along a first direction substantially perpendicular to the planar surface;
a plurality of channel regions, each being provided between and in contact with both the common drain region and the common source region;
a plurality of regions of charge-trapping material each provided associated with and in contact with a respective one of the channel regions; and
a plurality of gate electrodes that are spaced apart from each other and insulated from each other by a dielectric material, each gate electrode being positioned to be adjacent one of the channel regions, separated from that channel region by the associated region of charge-trapping material, each gate electrode extending lengthwise along a second direction substantially parallel the planar surface.

### Claim 3 (depends on 2)

The thin-film NOR memory string of claim 2, wherein the thin-film NOR memory string is formed in a semiconductor structure that further comprises:
a source line select transistor electrically coupled to the common source region and configured to receive a control signal that switches the source line select transistor between a conducting state and a non-conducting state; and
an interconnect conductor extending along a third direction substantially orthogonal to both the first and the second directions, the interconnect conductor electrically connecting the circuitry for supporting memory operations to the source line select transistor, such that, when the source line select transistor is in the conducting state, the common source region is electrically coupled to the circuitry for memory operations through the interconnect conductor.

### Claim 4 (depends on 3)

The thin-film NOR memory string of claim 3, wherein the interconnect conductor is provided above the thin-film NOR memory string.

### Claim 5 (depends on 4)

The thin-film NOR memory string of claim 4, wherein the source line select transistor comprises a thin-film transistor having a source region, a channel region and a drain region that are stacked along the first direction.

### Claim 6 (depends on 2)

The thin-film NOR memory string of claim 2, wherein the circuitry in the circuitry for supporting memory operations comprises one or more voltage sources.

### Claim 7 (depends on 2)

The thin-film NOR memory string of claim 2, wherein the thin-film NOR memory string is one thin-film NOR memory string in an array of thin-film NOR memory strings.

### Claim 8 (depends on 2)

A memory structure formed above a planar surface of a semiconductor substrate, the semiconductor substrate including circuitry formed therein or thereon for supporting memory circuit operations, comprising:
an array of thin-film NOR memory strings including first, second and third thin-film NOR memory strings, the first, the second and the third thin-film NOR memory strings each being configured substantially as the thin-film NOR memory string of claim 2; and
first, second and third conductor segments, wherein (a) the first conductor segment is electrically connected to both the common drain region of the first thin-film NOR memory string and the common drain terminal of the second thin-film NOR memory string, (b) the second conductor segment is electrically connected to the common drain region of the third thin-film NOR memory string, and (c) the third conductor segment is electrically connected to the circuitry for supporting memory operations; and
first and second bit-line select transistors each configured to receive a control signal that causes the bit-line select transistor to switch between a conducting state and a non-conductive state, wherein (i) when the first bit-line select transistor is biased to its conducting state, the first bit-line select transistor connects the first conductor segment to the third conductor segment, and (ii) when the second bit-line select transistor is biased to its conducting state, the second bit-line select transistor connects the second conductor segment to the third conductor segment,

### Claim 9 (depends on 8)

The memory structure of claim 8, wherein the first and second conductor segments are provided between any one of the first, the second and the third thin-film NOR memory strings and the planar surface of the semiconductor substrate.

### Claim 10 (depends on 8)

The memory structure of claim 8, wherein both the first and the second bit-line select transistors are formed in the semiconductor substrate.

### Claim 11 (depends on 8)

The memory structure of claim 8, wherein the first, the second and the third conductor segments are each provided above the thin-film NOR memory strings.

### Claim 12 (depends on 11)

The memory structure of claim 11, wherein both the first and the second bit-line select transistors are formed between the first and the third conductor segments.

### Claim 13 (depends on 8)

The memory structure of claim 8, wherein the first bit-line select transistor and the second bit line select transistor each comprise a thin-film transistor having a source region, a channel region and a drain region that are stacked along the first direction.

### Claim 14 (depends on 8)

The memory structure of claim 8, further comprising:
first, second and third source line select transistors electrically coupled respectively to the common source regions of the first, the second and the third thin-film NOR memory strings, each source line select transistor having a control terminal configured for receiving a control signal that switches the source line select transistor between a conducting state and a non-conducting state; and
first and second interconnect conductors each electrically coupled to the circuitry for supporting memory operations and each extending along a third direction substantially orthogonal to both the first and second directions, wherein the first interconnect conductor is electrically coupled to both the first and second source line select transistors and the second interconnect conductor is electrically coupled to the third source line select transistor, such that, when any of the first, the second and the third source line select transistors is in its conducting state, the common source region of the respective thin-film NOR memory string is electrically coupled to the circuitry for supporting memory operations through its electrically coupled source line select transistor.

### Claim 15 (depends on 14)

The memory structure of claim 14, wherein the first and the second interconnect conductors are provided above at least one of the first, the second and the third thin-film NOR memory strings.

### Claim 16 (depends on 14)

The memory structure of claim 14, further comprising a fourth thin-film NOR memory string (“charging column”) configured substantially the same as the first thin-film NOR memory string, the fourth thin-film NOR memory string having a common source region electrically coupled to the first and second interconnect conductors and a common drain region electrically coupled to the circuitry for supporting memory operations, wherein the charging column provides a current drawn from the circuitry for supporting memory operations to pre-charge any common source region electrically coupled to the first or the second interconnect conductor by its source line select transistor, prior to a read, programming or erase operation.

### Claim 17 (depends on 16)

The memory structure of claim 16, wherein one or more of the channel regions in the charging column are conducting during the pre-charging.

### Claim 18 (depends on 16)

The memory structure of claim 16, further comprising, a source-line select transistor that connects the circuitry for supporting memory operations to the fourth interconnect conductor.

### Claim 19 (depends on 14)

The memory structure of claim 14, wherein the first and the second interconnect conductors are each one interconnect conductor in a group of conductor segments formed in plane substantially parallel to the planar surface.

### Claim 20 (depends on 8)

The memory structure of claim 8, wherein the array of thin-film NOR memory strings is organized as rows and columns of thin-film NOR memory string, each row of thin-film NOR memory strings extending along the third direction.

### Claim 21 (depends on 20)

The memory structure of claim 20, wherein the thin-film NOR memory strings within the array of thin-film NOR memory strings are isolated from each other by an isolation dielectric material or by an air gap.

### Claim 22 (depends on 8)

The memory structure of claim 8, wherein the gate electrode of each thin-film NOR memory string in the array of thin-film NOR memory strings terminates at a staircase structure and wherein each gate electrode is electrically coupled at the stair-case structure by conductor-filled vias to the circuitry for supporting memory operations.

### Claim 23 (depends on 8)

The memory structure of claim 8, wherein the common source regions of the first and the third thin-film NOR memory strings are implemented by the same semiconductor layer.

### Claim 24 (depends on 8)

The memory structure of claim 8, wherein the common drain regions of the first and the third thin-film NOR memory strings are implemented by the same semiconductor layer.

### Claim 25 (depends on 2)

The thin-film NOR memory string of claim 2, wherein the circuitry for supporting memory operations comprises sense amplifiers that are distributed throughout the planar surface of the semiconductor substrate.

### Claim 26 (depends on 2)

The thin-film NOR memory string of claim 2, further comprising a pre-charge transistor that, when biased to a conducting state, electrically connects the common source region and the common drain region.

### Claim 27 (depends on 2)

The thin-film NOR memory string of claim 2, wherein the circuitry for supporting memory operation comprises a body bias voltage source, wherein the channel regions of the thin-film NOR memory string are connected to the body bias voltage source.

### Claim 28 (depends on 2)

The thin-film NOR memory string of claim 2, wherein the gate electrodes are insulated from each other by an isolation dielectric material or air gap.

### Claim 29 (depends on 8)

A composite memory structure comprising first and second modular memory structures provided one on top of the other, wherein each modular memory structure comprises a memory structure as in the memory structure of claim 8.

### Claim 30 (depends on 29)

The composite memory structure of claim 29, wherein the first and second modular memory structures are isolated from each other by a dielectric layer.

### Claim 31 (depends on 30)

The composite memory structure of claim 30, wherein the thin-film NOR memory strings in the first and the second modular memory structures are aligned along the first direction and wherein the common source regions of corresponding thin-film NOR memory strings of the first and second modular memory structures are connected by conductor-filled vias through the dielectric layer.

### Claim 32 (depends on 2)

The thin-film NOR memory string of claim 2, further comprising metallic pylons embedded in both the common source region and the common drain region.

### Claim 33 (depends on 32)

The thin-film NOR memory string of claim 32, wherein the metallic pylons each comprises one or more of titanium nitride, tungsten nitride or tungsten.

### Claim 34 (depends on 32)

The thin-film NOR memory string of claim 32, wherein each metallic pylon is formed using an atomic layer deposition technique.

### Claim 35 (depends on 2)

The thin-film NOR memory string of claim 2, wherein the channel regions each comprise a first section and a second section, and wherein the first section serves as a channel region for one of the thin-film memory transistors of the thin-film NOR memory string and wherein the second section has a dopant concentration multiple times that of the first section.

### Claim 36 (depends on 2)

The thin-film NOR memory string of claim 2, wherein the common source region and the common drain region are each implemented by a plurality of electrically connected semiconductor layers.

### Claim 37 (depends on 2)

The thin-film NOR memory string of claim 2, wherein the charge-trapping material comprises one or more of: silicon nitride, conductive nanodots embedded in a non-conducting dielectric material, an isolated floating gate, and an oxide-nitride-oxide triple-layer.

### Claim 38 (depends on 2)

The thin-film memory structure of claim 2, wherein each region of the charge-trapping material is capped by a layer of blocking dielectric, or a high dielectric constant film.

### Claim 39 (depends on 38)

The thin-film NOR memory string of claim 38, wherein the high dielectric constant film comprises aluminum oxide, hafnium oxide or any combination thereof.

### Claim 40 (depends on 2)

The thin-film NOR memory string of claim 2, wherein each channel region is substantially semi-annular.

### Claim 41 (depends on 39)

The thin-film NOR memory string of claim 39, wherein the charge-trapping material forms an annular ring enclosing the channel regions.