# US 2021/0280602 A1 · Integrated Assemblies Having Vertically-Spaced Channel Material Segments, and Methods of Forming Integrated Assemblies

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- Number: US 2021/0280602 A1
- Document ID: US20210280602A1
- Status: Published application
- Kind: A1
- Application number: 17/315,951
- Filed: 2021-05-10
- Published: 2021-09-09
- Earliest claimed: 2019-06-06
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: John D. Hopkins; Shyam Surthi
- Web page: https://patentgrep.com/patent/US20210280602A1

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- H10B 41/10: characterised by the top-view layout
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 43/10: characterised by the top-view layout
- H10B 43/35: with cell select transistors, e.g. NAND
- H10D 30/689: {Vertical floating-gate IGFETs}
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10D 64/037: {comprising charge-trapping insulators}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have primary regions of a first vertical thickness, and have terminal projections of a second vertical thickness which is greater than the first vertical thickness. The terminal projections include control gate regions. Charge-blocking regions are adjacent the control gate regions, and are vertically spaced from one another. Charge-storage regions are adjacent the charge-blocking regions and are vertically spaced from one another. Gate-dielectric material is adjacent the charge-storage regions. Channel material is adjacent the gate dielectric material. Some embodiments included methods of forming integrated assemblies.

## Claims

### Claim at position 1

1-22. (canceled)

### Claim 23

A method of forming an integrated structure, comprising:
forming a vertical stack of alternating first and second levels; the first levels comprising first material, and the second levels comprising second material;
recessing the first levels relative to the second levels; the second levels having projecting terminal ends extending beyond the recessed first levels; the terminal ends having surfaces of the second material; the recessed first levels having surfaces of the first material;
forming third material along the second material selectively relative to the first material; the third material extending around the terminal ends of the second levels to widen the terminal ends; the widened terminal ends being vertically spaced from one another by gaps;
forming fourth material within the gaps; the third and fourth materials having outer surfaces that form a vertical edge; inner surfaces of the fourth material being adjacent the surfaces of the first material;
forming charge-storage material extending vertically along the vertical edge;
forming gate-dielectric material extending vertically along the charge-storage material;
forming channel material extending vertically along the gate-dielectric material;
removing the second and third materials to leave first voids;
forming conductive levels within the first voids; the conductive levels having primary regions of a first vertical thickness, and having terminal projections of a second vertical thickness which is greater than the first vertical thickness;
removing the first and fourth materials to leave second voids; and
extending the second voids through the charge-storage material to divide the charge-storage material into vertically-spaced segments.

### Claim 24 (depends on 23)

The method of claim 23 further comprising at least partially filling the second voids with insulative material.

### Claim 25 (depends on 23)

The method of claim 23 wherein the conductive levels only partially fill the first voids, and wherein regions of the first voids remain within the terminal projections of the conductive levels.

### Claim 26 (depends on 23)

The method of claim 23 further comprising forming charge-blocking material extending along the third material; and wherein the forming of the charge-storage material comprises forming the charge-storage material to extend vertically along the charge-blocking material.

### Claim 27 (depends on 23)

The method of claim 23 further comprising forming charge-blocking material extending along the third material; and wherein:
the forming of the charge-storage material comprises forming the charge-storage material to extend vertically along the charge-blocking material;
the vertically-spaced segments of the charge-storage material are vertically-spaced second segments; and
the extending of the second voids comprises extending the second voids through the charge-blocking material to divide the charge-blocking material into vertically-spaced first segments.

### Claim 28 (depends on 23)

The method of claim 23 further comprising forming a fifth material around the widened terminal ends prior to forming the fourth material.

### Claim 29 (depends on 28)

The method of claim 28 wherein the fifth material comprises one or both of silicon oxynitride and silicon dioxide.

### Claim 30 (depends on 28)

The method of claim 28 wherein the fifth material is formed to extend across the gaps and along the first surfaces.

### Claim 31 (depends on 28)

The method of claim 28 wherein the charge-storage material is formed directly against the fifth material.

### Claim 32 (depends on 28)

The method of claim 28 wherein the fifth material is charge-blocking material, and wherein additional charge-blocking material is formed along the fifth material prior to forming the charge-storage material.

### Claim 33 (depends on 23)

The method of claim 23 wherein the second and third materials are a same composition as one another.

### Claim 34 (depends on 33)

The method of claim 33 wherein the second and third materials comprise silicon nitride, and wherein the first material comprises silicon dioxide.

### Claim 35 (depends on 34)

The method of claim 34 wherein the fourth material consists essentially of silicon.