# US 2021/0280598 A1 · Memory device

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- Number: US 2021/0280598 A1
- Document ID: US20210280598A1
- Status: Published application
- Kind: A1
- Application number: 17/324,413
- Filed: 2021-05-19
- Published: 2021-09-09
- Earliest claimed: 2019-09-06
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Satoshi NAGASHIMA
- Web page: https://patentgrep.com/patent/US20210280598A1

## CPC

- A61B 90/361: {Image-producing devices, e.g. surgical cameras}
- A61B 34/30: Surgical robots
- A61B 90/25: Supports therefor
- G02B 7/001: {Counterbalanced structures, e.g. surgical microscopes}
- G03B 15/14: for taking photographs during medical operations
- G03B 17/561: {Support related camera accessories}
- H04N 23/54: Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
- H04N 23/695: Control of camera direction for changing a field of view, e.g. pan, tilt or based on tracking of objects
- H10B 41/10: characterised by the top-view layout
- H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 43/10: characterised by the top-view layout
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/35: with cell select transistors, e.g. NAND
- A61B 90/37: {Surgical systems with images on a monitor during operation}
- A61B 2017/00017: {Electrical control of surgical instruments}
- A61B 2017/00973: {pedal-operated}
- A61B 2034/2059: {Mechanical position encoders}
- A61B 2090/304: {using chemi-luminescent materials}
- A61B 2090/371: {with simultaneous use of two cameras}
- A61B 2090/504: {with a counterweight}
- A61B 2090/506: {using a parallelogram linkage, e.g. panthograph}
- A61B 2090/508: {with releasable brake mechanisms}
- A61B: DIAGNOSIS; SURGERY; IDENTIFICATION (usefulness limited to only animals A61D)
- G02B: OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G03B: APPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR (optical parts of such apparatus G02B; photosensitive materials or processes for photographic purposes G03C; apparatus for processing exposed photographic materials G03D)
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A memory device includes a first and second conductor respectively included in a first and second layer stack stacked in a first direction and separated from each other; a first and second portion of a semiconductor extending in the first direction between the first and the second layer stack, and separated from each other in same layer; a first film between the first conductor and the first portion; a second film between the second conductor and the second portion; a first insulator between the first conductor and the first film; a second insulator between the second conductor and the second film; a third insulator between the first insulator and the first film; and a fourth insulator between the second insulator and the second film. The third and fourth insulator have a higher dielectric constant than the first and second insulator.

## Claims

### Claim 1

A memory device comprising:
a first conductor included in a first layer stack that is stacked in a first direction;
a second conductor included in a second layer stack that is stacked in the first direction and included in a layer that includes the first conductor, the second layer stack being separated from the first layer stack;
a first semiconductor between the first layer stack and the second layer stack, the first semiconductor including:
a first portion and a second portion, each extending in the first direction, and being separated from each other in same layer; and
a third portion electrically coupling the first portion and the second portion below the first conductor and the second conductor;
a first charge storage film between the first conductor and the first portion of the first semiconductor;
a second charge storage film between the second conductor and the second portion of the first semiconductor;
a first insulator between the first conductor and the first charge storage film;
a second insulator between the second conductor and the second charge storage film;
a third insulator between the first insulator and the first charge storage film; and
a fourth insulator between the second insulator and the second charge storage film,
wherein
the third insulator and the fourth insulator have a dielectric constant higher than that of the first insulator and the second insulator.

### Claim 2 (depends on 1)

The memory device according to claim 1, further comprising
a third conductor stacked above the first conductor in the first direction;
a fourth conductor stacked above the second conductor in the first direction, and separated from the third conductor in same layer;
a third charge storage film between the third conductor and the first portion of the first semiconductor;
a fourth charge storage film between the fourth conductor and the second portion of the first semiconductor;
a fifth insulator between the third conductor and the third charge storage film;
a sixth insulator between the fourth conductor and the fourth charge storage film;
a seventh insulator between the fifth insulator and the third charge storage film; and
an eighth insulator between the sixth insulator and the fourth charge storage film,
wherein
the seventh insulator and the eighth insulator have a dielectric constant higher than that of the fifth insulator and the sixth insulator.

### Claim 3 (depends on 2)

The memory device according to claim 2, wherein
the third insulator and the seventh insulator are separated from each other; and
the fourth insulator and the eighth insulator are separated from each other.

### Claim 4 (depends on 1)

The memory device according to claim 1, further comprising a second semiconductor on a top surface of the first portion of the first semiconductor and on a top surface of the second portion of the first semiconductor above the first conductor and the second conductor.

### Claim 5 (depends on 1)

The memory device according to claim 1, wherein the first charge storage film and the second charge storage film include polysilicon or metal.

### Claim 6 (depends on 5)

The memory device according to claim 5, wherein the third insulator and the fourth insulator include hafnium (Hf) or zirconium (Zr).

### Claim 7 (depends on 1)

The memory device according to claim 1, further comprising:
a first sacrificial member arranged alongside the third insulator between the first insulator and the first charge storage film; and
a second sacrificial member arranged alongside the fourth insulator between the second insulator and the second charge storage film;
wherein
the first sacrificial member includes a first oxide film being in contact with the first charge storage film, and a first nitride film being in contact with the first insulator; and
the second sacrificial member includes a second oxide film being in contact with the second charge storage film, and a second nitride film being in contact with the second insulator.

### Claim 8 (depends on 7)

The memory device according to claim 7, further comprising:
a ninth insulator separating, into two portions, each of the first semiconductor, the first charge storage film, the second charge storage film, the first insulator, the second insulator, the third insulator, and the fourth insulator; and
a tenth insulator separating, into two portions, each of the first semiconductor, the first charge storage film, the second charge storage film, the first insulator, the second insulator, the first sacrificial member, and the second sacrificial members.

### Claim 9 (depends on 7)

The memory device according to claim 7, wherein the first oxide film and the second oxide film include boron (B) or phosphorus (P).

### Claim 10 (depends on 1)

The memory device according to claim 1, wherein
the first layer stack, the first insulator, the third insulator, the first charge storage film, the first portion of the first semiconductor, the second portion of the first semiconductor, the second charge storage film, the fourth insulator, the second insulator, and the second layer stack are arranged in this order in a second direction in a stack surface of the first layer stack and the second layer stack; and
the first insulator, the third insulator, the first charge storage film, the first portion of the first semiconductor, the second portion of the first semiconductor, the second charge storage film, the fourth insulator, and the second insulator extend in a third direction intersecting the second direction in the stack surface.

### Claim 11 (depends on 10)

The memory device according to claim 10, wherein the first semiconductor, the first charge storage film, and the second charge storage film are shorter in the third direction than the third insulator and the fourth insulator.

### Claim 12 (depends on 11)

The memory device according to claim 11, wherein the first semiconductor is shorter in the third direction than the first charge storage film and the second charge storage film.

### Claim 13 (depends on 12)

The memory device according to claim 12, wherein the first charge storage film and the second charge storage film include boron (B) or carbon (C).

### Claim 14 (depends on 10)

The memory device according to claim 10, further comprising two ninth insulators each extending in the third direction, and separating, into two portions, each of the first semiconductor, the first charge storage film, the second charge storage film, the first insulator, the second insulator, the third insulator, and the fourth insulator, wherein
a portion of the first conductor sandwiched between the two ninth insulators has a length in the third direction shorter than that of the first charge storage film and the second charge storage film in the third direction.

### Claim 15 (depends on 10)

The memory device according to claim 10, wherein each of the first semiconductor, the first charge storage film, and the second charge storage film are gradually thinned toward an end in the third direction.