# US 2021/0280591 A1 · Non-volatile memory (nvm) cell structure to increase reliability

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2021/0280591 A1
- Document ID: US20210280591A1
- Status: Published application
- Kind: A1
- Application number: 16/807,537
- Filed: 2020-03-03
- Published: 2021-09-09
- Earliest claimed: 2020-03-03
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Shih-Hsien Chen; Chun-Yao Ko; Felix Ying-Kit Tsui
- Web page: https://patentgrep.com/patent/US20210280591A1

## CPC

- H10B 41/35: with a cell select transistor, e.g. NAND
- G11C 16/0408: {comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/0433: {comprising cells containing a single floating gate transistor and one or more separate select transistors}
- G11C 16/0441: {comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates}
- G11C 16/10: Programming or data input circuits
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- H10D 1/692: {Electrodes}
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling}
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Various embodiments of the present disclosure are directed towards a memory cell including first and second storage transistors. A first capacitor includes a first capacitor active region disposed within a substrate and a capacitor plate comprised of a first floating gate portion of a floating gate. A second capacitor includes a second capacitor active region disposed within the substrate and a capacitor plate comprised of a second floating gate portion of the floating gate. The first storage transistor includes source/drain regions disposed within a bit line write region and a first gate electrode comprised of a third floating gate portion of the floating gate. The second storage transistor includes source/drain regions disposed within a bit line read region and a second gate electrode comprised of a fourth floating gate portion of the floating gate. The bit line read and write regions are offset from one another by a non-zero distance.

## Claims

### Claim 1

A memory cell comprising:
a first capacitor including a first capacitor plate comprised of a first capacitor active region disposed within a substrate and a second capacitor plate comprised of a first floating gate portion of a floating gate, wherein the floating gate overlies the substrate, and wherein the first capacitor active region is a doped region of the substrate and comprises a first doping type;
a second capacitor including a first capacitor plate comprised of a second capacitor active region disposed within the substrate and a second capacitor plate comprised of a second floating gate portion of the floating gate;
a plurality of transistors overlying the substrate, wherein the transistors include:
a first storage transistor including source/drain regions disposed within a bit line write region and a first gate electrode comprised of a third floating gate portion of the floating gate, wherein the bit line write region is disposed within the substrate; and
a second storage transistor including source/drain regions disposed within a bit line read region and a second gate electrode comprised of a fourth floating gate portion of the floating gate, wherein the bit line read region is disposed within the substrate and is laterally offset from the bit line write region by a non-zero distance.

### Claim 2 (depends on 1)

The memory cell of claim 1, wherein the first floating gate portion, the second floating gate portion, the third floating gate portion, and the fourth floating gate portion are laterally offset from one another by non-zero distances.

### Claim 3 (depends on 1)

The memory cell of claim 1, wherein the first capacitor active region is disposed within a first well region, wherein the bit line write and read regions are disposed within a second well region, and the second capacitor active region is disposed within a third well region.

### Claim 4 (depends on 3)

The memory cell of claim 3, wherein the first well region, the second well region, and the third well region are laterally offset from one another by non-zero distances.

### Claim 5 (depends on 1)

The memory cell of claim 1, wherein the floating gate is a single continuous conductive material that continuously laterally extends from the first capacitor active region to the second capacitor active region.

### Claim 6 (depends on 1)

The memory cell of claim 1, wherein the first storage transistor is configured to perform a program operation on the memory cell and the second storage transistor is configured to perform a read operation on the memory cell.

### Claim 7 (depends on 1)

The memory cell of claim 1, wherein the plurality of transistors are each configured as an n-channel metal oxide semiconductor (nMOS) transistor.

### Claim 8 (depends on 1)

The memory cell of claim 1, wherein the plurality of transistors further comprise:
a first selector transistor including source/drain regions disposed within the bit line write region and a first select gate electrode comprised of a first select gate portion of a select gate; and
a second selector transistor including source/drain regions disposed within the bit line read region and a second select gate electrode comprised of a second select gate portion of the select gate.

### Claim 9 (depends on 8)

The memory cell of claim 8, wherein the first selector transistor and the first storage transistor share a first common source/drain region disposed laterally between the floating gate and the select gate, wherein the second selector transistor and the second storage transistor share a second common source/drain region disposed laterally between the floating gate and the select gate, wherein the first common source/drain region is laterally offset from the second common source/drain region.

### Claim 10 (depends on 8)

The memory cell of claim 8, wherein the bit line write region and the bit line read region are laterally spaced between sidewalls of the select gate.

### Claim 11

An integrated circuit comprising:
a plurality of capacitors including a first capacitor and a second capacitor, wherein the first capacitor has a first capacitor electrode comprised of a first segment of a floating gate and the second capacitor has a second capacitor electrode comprised of a second segment of the floating gate; and
a plurality of transistors including a first storage transistor, a second storage transistor, a first select transistor, and a second select transistor, wherein source/drain regions of the first storage transistor and the first select transistor are disposed within a bit line write region and source/drain regions of the second storage transistor and the second select transistor are disposed within a bit line read region, wherein the bit line write region and the bit line read region are disposed within a substrate and are laterally offset from one another, wherein the first and second capacitor electrodes are configured as a gate electrode for both the first and second storage transistors.

### Claim 12 (depends on 11)

The integrated circuit of claim 11, wherein the first storage transistor and the first select transistor are electrically coupled in series, wherein the second storage transistor and the second select transistor are electrically coupled in series.

### Claim 13 (depends on 11)

The integrated circuit of claim 11, wherein the first and second select transistors comprise a select gate that overlies both the bit line read region and the bit line write region.

### Claim 14 (depends on 13)

The integrated circuit of claim 13, wherein the first storage transistor and the first select transistor comprise a common source/drain region disposed within the bit line write region and spaced laterally between the floating gate and the select gate.

### Claim 15 (depends on 11)

The integrated circuit of claim 11, wherein the first storage transistor and the first select transistor are configured to perform a program operation on the floating gate, wherein the second storage transistor and the second select transistor are configured to perform a read operation on the floating gate.

### Claim 16 (depends on 11)

The integrated circuit of claim 11, wherein the bit line write region and the bit line read region are disposed within a well region of the substrate, wherein the well region comprises a first doping type and the bit line write and read regions both comprise a second doping type opposite the first doping type.

### Claim 17

A method for forming a memory device, the method comprising:
doping a substrate to form a first well region, a second well region, and a third well region within the substrate, wherein the second well region is spaced laterally between the first and third well regions;
depositing a floating gate dielectric structure over the substrate;
forming a floating gate over the floating gate dielectric structure, wherein the floating gate continuously laterally extends from the first well region to the third well region; and
doping the substrate to form a bit line read region and a bit line write region within the second well region, wherein the bit line read region includes source/drain regions on opposite sides of the floating gate and the bit line write region includes source/drain regions on the opposite sides of the floating gate, wherein the source/drain regions of the bit line read region are laterally offset from the source/drain regions of the bit line write region by a non-zero distance.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
doping the substrate to form a first capacitor active region within the first well region; and
doping the substrate to form a second capacitor active region within the third well region.

### Claim 19 (depends on 18)

The method of claim 18, wherein the first capacitor active region, the second capacitor active region, the bit line read region, and the bit line write region are formed concurrently.

### Claim 20 (depends on 17)

The method of claim 17, further comprising:
depositing a select gate dielectric structure over the second well region; and
forming a select gate over the select gate dielectric structure, wherein the select gate is laterally offset from the floating gate and abuts a source/drain region within the bit line read region and a source/drain region within the bit line write region.