# US 2021/0280588 A1 · Anti-fuse device method and layout

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- Number: US 2021/0280588 A1
- Document ID: US20210280588A1
- Status: Published application
- Kind: A1
- Application number: 17/317,162
- Filed: 2021-05-11
- Published: 2021-09-09
- Earliest claimed: 2018-08-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Min-Shin WU; Meng-Sheng CHANG; Shao-Yu CHOU; Yao-Jen YANG
- Web page: https://patentgrep.com/patent/US20210280588A1

## CPC

- G11C 17/18: Auxiliary circuits, e.g. for writing into memory
- H10W 20/491: {Antifuses, i.e. interconnections changeable from non-conductive to conductive}
- G11C 17/16: using electrically-fusible links
- H10B 20/25: One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method of manufacturing an anti-fuse device includes forming an anti-fuse structure on a substrate, forming a first transistor at a first position away from the anti-fuse device in a first direction, and forming a second transistor at a second position away from the anti-fuse device in a second direction opposite the first direction. Forming the anti-fuse structure includes forming first and second S/D structures in an active area, the first transistor includes the first S/D structure, and the second transistor includes the second S/D structure. The method includes constructing a first electrical connection between gate structures of the first and second transistors and a second electrical connection between a third S/D structure of the first transistor and a fourth S/D structure of the second transistor.

## Claims

### Claim 1

A method of manufacturing an anti-fuse device, the method comprising:
forming an anti-fuse structure on a substrate, the forming the anti-fuse structure comprising forming first and second source/drain (S/D) structures in an active area;
forming a first transistor at a first position away from the anti-fuse device in a first direction, the first transistor including the first S/D structure;
forming a second transistor at a second position away from the anti-fuse device in a second direction opposite the first direction, the second transistor including the second S/D structure;
constructing a first electrical connection between gate structures of the first and second transistors; and
constructing a second electrical connection between a third S/D structure of the first transistor and a fourth S/D structure of the second transistor.

### Claim 2 (depends on 1)

The method of claim 1, wherein the constructing the first electrical connection comprises:
forming a first via structure on the gate structure of the first transistor;
forming a second via structure on the gate structure of the second transistor; and
forming a conductive element overlying and electrically connected to each of the first and second via structures.

### Claim 3 (depends on 2)

The method of claim 2, wherein the forming the conductive element comprises:
forming the conductive element overlying the substrate at a position away from the active area in a third direction perpendicular to the first and second directions.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
forming a third via structure on a gate structure of the anti-fuse structure, the third via structure overlying the substrate at a position away from the active area in a fourth direction opposite the third direction.

### Claim 5 (depends on 1)

The method of claim 1, wherein the constructing the second electrical connection between the third and fourth S/D structures comprises forming a first contact structure on the third S/D structure and a second contact structure on the fourth S/D structure.

### Claim 6 (depends on 5)

The method of claim 5, wherein the constructing the second electrical connection between the third and fourth S/D structures further comprises forming a conductive element electrically connected to each of the first and second contact structures and overlying each of the anti-fuse structure, the first and second transistors, and the first and second contact structures.

### Claim 7 (depends on 1)

The method of claim 1, wherein the constructing the first electrical connection between the gate structures of the first and second transistors is part of constructing a plurality of electrical connections between gate structures of corresponding pluralities of first and second transistors of an anti-fuse device array.

### Claim 8

A method of manufacturing an anti-fuse device, the method comprising:
forming a plurality of source/drain (S/D) structures in an active area of a substrate;
forming first and second transistors, the first and second transistors sharing a first S/D structure of the plurality of S/D structures;
forming a first anti-fuse structure, the first anti-fuse structure and the first transistor sharing a second S/D structure of the plurality of S/D structures;
forming a second anti-fuse structure, the second anti-fuse structure and the second transistor sharing a third S/D structure of the plurality of S/D structures;
forming a third transistor, the third transistor and the first anti-fuse structure sharing a fourth S/D structure of the plurality of S/D structures; and
forming a fourth transistor, the fourth transistor and the second anti-fuse structure sharing a fifth S/D structure of the plurality of S/D structures.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
constructing a first electrical connection between gate structures of the first and third transistors; and
constructing a second electrical connection between gate structures of the second and fourth transistors.

### Claim 10 (depends on 9)

The method of claim 9, wherein
the constructing the first electrical connection comprises forming a first conductive element in a first conductive layer and overlying the gate structures of the first and third transistors,
the constructing the second electrical connection comprises forming a second conductive element in the first conductive layer and overlying the gate structures of the second and fourth transistors, and
the first and second conductive elements are aligned in a first direction.

### Claim 11 (depends on 9)

The method of claim 9, wherein
the constructing the first electrical connection comprises forming a first conductive element in a first conductive layer and overlying the gate structures of the first and third transistors,
the constructing the second electrical connection comprises forming a second conductive element in the first conductive layer and overlying the gate structures of the second and fourth transistors,
the first conductive element is positioned away from the active area in a first direction, and
the second conductive element is positioned away from the active area in a second direction opposite the first direction.

### Claim 12 (depends on 8)

The method of claim 8, further comprising:
forming a first contact structure on the first S/D structure of the plurality of S/D structures;
forming a second contact structure on a sixth S/D structure of the plurality of S/D structures included in the third transistor;
forming a third contact structure on a seventh S/D structure of the plurality of S/D structures included in the fourth transistor; and
constructing an electrical connection between the first, second, and third contact structures.

### Claim 13 (depends on 12)

The method of claim 12, wherein the constructing the electrical connection between the first, second, and third contact structures comprises forming a conductive element electrically connected to each of the first, second, and third contact structures and overlying each of the first and second anti-fuse structures, the first through fourth transistors, and the first, second, and third contact structures.

### Claim 14

A method of generating an integrated circuit (IC) layout diagram, the method comprising:
intersecting an active region with first, second, and third gate regions, thereby defining a location of a first anti-fuse structure between first and second transistors;
overlying the active region with first and second contact regions, the first, second, and third gate regions being between the first and second contact regions;
overlying the active region and first and second contact regions with a first conductive region; and
storing the IC layout diagram comprising the active region, the first, second, and third gate regions, the first and second contact regions, and the first conductive region in a storage device.

### Claim 15 (depends on 14)

The method of claim 14, wherein
the first gate region corresponds to the first transistor,
the second gate region corresponds to the first anti-fuse structure,
the third gate region corresponds to the second transistor, and
the method further comprises:
overlying each of the first and third gate regions with a via region at a location away from the active region in a first direction; and
overlying the second gate region with a via region at a location away from the active region in a second direction opposite the first direction.

### Claim 16 (depends on 14)

The method of claim 14, further comprising:
intersecting the active region with fourth, fifth, and sixth gate regions, thereby defining a location of a second anti-fuse structure between third and fourth transistors; and
overlying the active region with a third contact region, the fourth, fifth, and sixth gate regions being between the second and third contact regions,
wherein the overlying the active region with the first conductive region comprises overlying the third contact region with the first conductive region.

### Claim 17 (depends on 16)

The method of claim 16, wherein
the first gate region corresponds to the first transistor,
the second gate region corresponds to the first anti-fuse structure,
the third gate region corresponds to the second transistor,
the fourth gate region corresponds to the third transistor,
the fifth gate region corresponds to the second anti-fuse structure,
the sixth gate region corresponds to the fourth transistor, and
the method further comprises:
overlying the first through sixth gate regions with respective first through sixth via regions;
overlying the first and third via regions with a second conductive region; and
overlying the fourth and sixth via regions with a third conductive region.

### Claim 18 (depends on 17)

The method of claim 17, wherein the overlying the first and third via regions with the second conductive region and the fourth and sixth via regions with the third conductive region comprises aligning the second and third conductive regions along a first direction.

### Claim 19 (depends on 17)

The method of claim 17, wherein
the overlying the first and third via regions with the second conductive region comprises aligning the second conductive region and the fifth via region along a first direction, and
the overlying the fourth and sixth via regions with the third conductive region comprises aligning the third conductive region and the second via region along the first direction.

### Claim 20 (depends on 14)

The method of claim 14, further comprising placing the IC layout diagram in an IC layout diagram of an anti-fuse array.