# US 2021/0280587 A1 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0280587 A1 - Document ID: US20210280587A1 - Status: Published application - Kind: A1 - Application number: 16/992,265 - Filed: 2020-08-13 - Published: 2021-09-09 - Earliest claimed: 2020-03-05 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Hiroaki YAMAMOTO; Shinichi Asou; Kenichi Kawabata; Haruyuki Miyata; Takahiro Shimokawa; Takaco Umezawa; Syunsuke Sasaki - Web page: https://patentgrep.com/patent/US20210280587A1 ## CPC - H10B 10/12: {comprising a MOSFET load element} - H10D 89/10: Integrated device layouts - G11C 11/412: using field-effect transistors only - G11C 11/417: for memory cells of the field-effect type - H10B 10/18: {Peripheral circuit regions} - H10B 43/40: characterised by the peripheral circuit region - G11C 16/0483: {comprising cells having several storage transistors connected in series} - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract According to one embodiment, a semiconductor memory device includes, on a substrate, a memory region 600 and a peripheral circuit region 500 in which an MOS transistor 100 is formed. The MOS transistor 100 includes a drain region 120 and a source region 130 disposed in a first direction parallel to a surface of the substrate. On a surface of the drain region 120, a drain electrode 121 is formed to be connected with a contact plug 122. Further, on a surface of the source region 130, a source electrode 131 is formed to be connected with a contact plug 132. When viewed in the first direction, the drain electrode 121 has a region that does not overlap with the source electrode 131, and the source electrode 131 has a region that does not overlap with the drain electrode 121. ## Claims ### Claim 1 A semiconductor memory device comprising: a memory region on a semiconductor substrate, in which a memory cell array is formed; and a peripheral circuit region on the semiconductor substrate, in which a peripheral circuit is formed, wherein the peripheral circuit region is formed with at least one MOS transistor, the MOS transistor includes a first diffusion layer and a second diffusion layer that are disposed with a predetermined interval in a first direction parallel to a surface of the semiconductor substrate, the MOS transistor further including at least one gate wiring disposed between the first diffusion layer and the second diffusion layer, the at least one gate extending in a second direction orthogonal to the first direction, a first contact region is formed on a surface of the first diffusion layer, the first contact region being connected with a first plug configured to electrically connect the first diffusion layer and a first wiring formed in a wiring layer located vertically above the semiconductor substrate, a second contact region is formed on a surface of the second diffusion layer, the second contact region being connected with a second plug configured to electrically connect the second diffusion layer and a second wiring formed in the wiring layer, and when viewed in the first direction, the first contact region has a region that does not overlap with the second contact region, and the second contact region has a region that does not overlap with the first contact region. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein the first diffusion layer and the second diffusion layer are formed in an active region formed in the semiconductor substrate, and the gate wiring extends outside the active region, one end of the gate wiring includes at least one bent portion that bends in the first direction outside the active region, and a third contact region is formed on a tip side from the bent portion and is connected with a third plug configured to electrically connect the gate wiring and a third wiring formed on the wiring layer, and the gate wiring is bent toward a side, which is farther from the bent portion, of the first contact region and the second contact region. ### Claim 3 (depends on 2) The semiconductor memory device according to claim 2, wherein in the active region, two of the MOS transistors sharing the first diffusion layer are disposed in the first direction, and the bent portion formed in the gate wiring of one of the MOS transistors and the bent portion formed in another MOS transistor are disposed on the same side as the active region in the second direction. ### Claim 4 (depends on 2) The semiconductor memory device according to claim 2, wherein in the active region, two of the MOS transistors sharing the first diffusion layer are disposed in the first direction, and the bent portion formed in the gate wiring of one of the MOS transistors and the bent portion formed in the gate wiring of another MOS transistor are disposed with the active region interposed between the bent portions. ### Claim 5 (depends on 2) The semiconductor memory device according to claim 2, wherein in the active region, a plurality of the MOS transistors are disposed in the first direction, and two of the bent portions formed in the gate wirings of two of the MOS transistors adjacent to each other are disposed with the active region interposed between the bent portions. ### Claim 6 (depends on 2) The semiconductor memory device according to claim 2, wherein the memory cell array includes a memory string in which a plurality of memory cells are connected in series, and the plurality of memory cells are stacked in a direction perpendicular to the semiconductor substrate. ### Claim 7 (depends on 1) The semiconductor memory device according to claim 1, wherein the memory cell array includes: a conductor pillar that extends in a third direction orthogonal to the first direction and the second direction; and a plurality of word lines disposed on the semiconductor substrate and stacked in the third direction, memory cells are formed at locations in the conductor pillar, the locations respectively facing the plurality of word lines, and the first plug and the second plug have a length in the third direction larger than a distance between each of the plurality of word lines on one side and each of the plurality of word lines on another side in the third direction.