# US 2021/0280583 A1 · Semiconductor structure and formation method thereof

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- Number: US 2021/0280583 A1
- Document ID: US20210280583A1
- Status: Published application
- Kind: A1
- Application number: 17/249,542
- Filed: 2021-03-04
- Published: 2021-09-09
- Earliest claimed: 2020-03-05
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Fei ZHOU
- Web page: https://patentgrep.com/patent/US20210280583A1

## CPC

- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/837: {comprising vertical IGFETs}
- H10D 84/8316: {the IGFETs characterised by having gate sidewall spacers specially adapted for integration}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure and a fabrication method of the semiconductor structure are provided in the present disclosure. The semiconductor structure includes a substrate, including a first region, a second region, and a third region between the first region and the second region; a first channel pillar on the first region and a second channel pillar on the second region; a first work function layer on the first region of the substrate and on a sidewall surface of the first channel pillar; and a second work function layer on the second region of the substrate and on a sidewall surface of the second channel pillar.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate, including a first region, a second region, and a third region between the first region and the second region;
a first channel pillar on the first region and a second channel pillar on the second region;
a first work function layer on the first region of the substrate and on a sidewall surface of the first channel pillar; and
a second work function layer on the second region of the substrate and on a sidewall surface of the second channel pillar.

### Claim 2 (depends on 1)

The structure according to claim 1, further including:
a first gate dielectric layer between the sidewall surface of the first channel pillar and the first work function layer,
a second gate dielectric layer between the sidewall surface of the second channel pillar and the second work function layer, and
a gate electrode layer on the first work function layer, the second work function layer, and the third region of the substrate.

### Claim 3 (depends on 1)

The structure according to claim 1, wherein:
the substrate includes a first opening at the third region and exposed by a surface of the substrate; and
a first dielectric layer is formed in the first opening and on the surface of the substrate.

### Claim 4 (depends on 1)

The structure according to claim 1, wherein:
the first work function layer is made of a material including titanium aluminide.

### Claim 5 (depends on 1)

The structure according to claim 1, wherein:
the second work function layer is made of a material including titanium nitride, tantalum nitride, or a combination thereof.

### Claim 6 (depends on 2)

The structure according to claim 2, wherein:
a material of the first gate dielectric layer includes a combination of silicon oxide and a high dielectric constant material; and
a material of the second gate dielectric layer includes a combination of silicon oxide and a high dielectric constant material.

### Claim 7 (depends on 1)

The structure according to claim 1, wherein:
the substrate includes a first source/drain doped layer containing first ions and a second source/drain doped layer containing second ions; and conductivity types of the first ions and the second ions are different.

### Claim 8

A method for fabricating a semiconductor structure, comprising:
providing a substrate, including a first region, a second region, and a third region between the first region and the second region;
forming a first channel pillar on the first region and a second channel pillar on the second region;
forming a first work function layer on the first region of the substrate and on a sidewall surface of the first channel pillar; and
forming a second work function layer on the second region of the substrate and on a sidewall surface of the second channel pillar.

### Claim 9 (depends on 8)

The method according to claim 8, further including:
forming a first gate dielectric layer between the sidewall surface of the first channel pillar and the first work function layer,
forming a second gate dielectric layer between the sidewall surface of the second channel pillar and the second work function layer, and
forming a gate electrode layer on the first work function layer, the second work function layer, and the third region of the substrate.

### Claim 10 (depends on 9)

The method according to claim 9, wherein:
forming the first gate dielectric layer and the first work function layer includes:
forming a first initial gate dielectric layer on the first channel pillar, and
forming a first initial work function layer on the first initial gate dielectric layer, on the first region of the substrate, and on a portion of the third region; and
forming the second gate dielectric layer and the second work function layer includes:
forming a second initial gate dielectric layer on the second channel pillar; and
forming a second initial work function layer on the second initial gate dielectric layer, on the second region of the substrate, and on a portion of the third region.

### Claim 11 (depends on 10)

The method according to claim 10, wherein forming the second initial work function layer includes:
forming a second initial work function material layer on the substrate, the first initial gate dielectric layer, and the second initial gate dielectric layer;
forming a second patterned layer on the second initial work function material layer at the second region and the portion of the third region; and
using the second patterned layer as a mask, etching the second initial work function material layer.

### Claim 12 (depends on 11)

The method according to claim 11, wherein forming the first initial work function layer includes:
forming a first initial work function material layer on the substrate, the first initial gate dielectric layer, and the second initial work function layer.

### Claim 13 (depends on 12)

The method according to claim 12, wherein forming the first initial work function layer further includes:
forming a first patterned layer on the first initial work function material layer at the first region and the portion of the third region; and
using the first patterned layer as a mask, etching the first initial work function material layer till a surface of the second initial work function layer is exposed.

### Claim 14 (depends on 10)

The method according to claim 10, wherein forming the first work function layer and the second work function layer further includes:
removing the first initial work function layer and the second initial work function layer on the third region.

### Claim 15 (depends on 14)

The method according to claim 14, wherein removing the first initial work function layer and the second initial work function layer on the third region of the substrate includes:
forming a first sidewall spacer on the first initial work function layer on the sidewall surface of the first channel pillar and on a portion of the first region of the substrate;
forming a second sidewall spacer on the second initial work function layer on the sidewall surface of the second channel pillar and on a portion of the second region of the substrate; and
using the first sidewall spacer and the second sidewall spacer as a mask, etching the first initial work function layer and the second initial work function layer till the first initial work function layer and the second initial work function layer on the third region are removed.

### Claim 16 (depends on 15)

The method according to claim 15, wherein forming the first sidewall spacer and the second sidewall spacer includes:
depositing a sidewall spacer material layer on the first initial work function layer and the second initial work function layer; and
etching back the sidewall spacer material layer till surfaces of the first initial work function layer and the second initial work function layer are exposed.

### Claim 17 (depends on 14)

The method according to claim 14, wherein forming the gate electrode layer includes:
after removing the first initial work function layer and the second initial work function layer on the third region, forming a gate electrode material layer on the first channel pillar, the second channel pillar, and the substrate; and
etching the gate electrode material layer on tops of the first channel pillar and the second channel pillar to form the gate electrode layer.

### Claim 18 (depends on 17)

The method according to claim 17, wherein forming the first gate dielectric layer and the second gate dielectric layer includes:
after etching the gate electrode material layer on the tops of the first channel pillar and the second channel pillar, etching an exposed first initial gate dielectric layer and an exposed second initial gate dielectric layer.

### Claim 19 (depends on 18)

The method according to claim 18, wherein after forming the first channel pillar and the second channel pillar and before forming the first work function layer and the second work function, the method further includes:
forming a first opening at the third region of the substrate and exposed by a surface of the substrate; and
forming a first dielectric layer in the first opening and on the surface of the substrate.