# US 2021/0280573 A1 · Semiconductor device and method for manufacturing same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0280573 A1 - Document ID: US20210280573A1 - Status: Published application - Kind: A1 - Application number: 17/260,702 - Filed: 2019-07-08 - Published: 2021-09-09 - Earliest claimed: 2018-07-18 - Assignees: Kabushiki Kaisha Tokai Rika Denki Seisakusho - Applicants: Kabushiki Kaisha Tokai-Rika-Denki-Seisakusho - Inventors: Yoshikazu KATAOKA - Web page: https://patentgrep.com/patent/US20210280573A1 ## CPC - H10D 89/611: {using diodes as protective elements} - H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) - H10D 8/80: PNPN diodes, e.g. Shockley diodes or break-over diodes - H10D 18/031: {of lateral or planar thyristors} - H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) - H10D 62/102: {Constructional design considerations for preventing surface leakage or controlling electric field concentration} - H10D 84/00: Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/83: of only insulated-gate FETs [IGFET] - H10W 10/00: Isolation regions in semiconductor bodies between components of integrated devices - H10W 10/01: {Manufacture or treatment} - H10D 8/01: Manufacture or treatment - H10D 18/251: {Lateral thyristors} - H10D 48/30: Devices controlled by electric currents or voltages - H10D 84/204: {of combinations of diodes or capacitors or resistors} - H10D 84/619: {Combinations of lateral BJTs and one or more of diodes, resistors or capacitors} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device including a protected element, a contact region, wiring, and a channel stopper region. The protected element is configured including a p-n junction diode between an anode region and a cathode region, and is arranged in an active layer of a substrate. The periphery of the diode is surrounded by an element isolation region. The contact region is arranged at a portion on a main face of the anode region, and is set with a same conductivity type as the anode region, and set with a higher impurity concentration than the anode region. The wiring is arranged over the diode. One end portion of the wiring is connected to the contact region and another end portion extends over a passivation film. The channel stopper region is arranged at a portion on the main face of the anode region under the wiring between the contact region and the element isolation region, and is set with an opposite conductivity type to the contact region. ## Claims ### Claim 1 A semiconductor device comprising: a protected element that is configured to include a p-n junction diode between an anode region and a cathode region, and arranged in an active layer of a substrate including the active layer formed over a substrate-support with an insulation layer interposed between the active layer and the substrate-support; an element isolation region that is arranged in the active layer so as to surround a periphery of the p-n junction diode and to electrically isolate the p-n junction diode from an element arranged at the periphery of the p-n junction diode; a contact region that is arranged at a portion on a main face of the anode region, set with a same conductivity type as the anode region, and set with a higher impurity concentration than the anode region; wiring arranged above the p-n junction diode with a passivation film between the p-n junction diode and the wiring, one end portion of the wiring being connected to the contact region and another end portion of the wiring extending over the passivation film; and a channel stopper region that is arranged at a portion on the main face of the anode region under the wiring between the contact region and the element isolation region, and set with an opposite conductivity type to the contact region. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the channel stopper region is also arranged not under the wiring at a portion bordering a periphery of the contact region or surrounding the entire periphery of the contact region. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the channel stopper region is arranged surrounding a periphery that extends around the anode region and the cathode region. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the channel stopper region is set with a lower impurity concentration than the contact region, and is set with a higher impurity concentration than the anode region. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein a junction depth of the channel stopper region to the anode region is set deeper than a depth from the main face of the contact region. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein: an impurity concentration of the channel stopper region is set the same as an impurity concentration of the cathode region, and a junction depth of the channel stopper region to the anode region is set the same as a junction depth of the cathode region to the anode region. ### Claim 7 A method for manufacturing a semiconductor device, the method comprising: forming an element isolation region so as to surround a forming region for a p-n junction diode configuring a protected element in an active layer of a substrate including the active layer formed over a substrate-support with an insulation layer interposed between the active layer and the substrate-support, and of forming an anode region in the active layer such that a periphery of the anode region is surrounded by the element isolation region; forming a cathode region having an opposite conductivity type to the anode region of the p-n junction diode on a portion on the main face of the anode region so as to form the p-n junction diode; forming a contact region set with the same conductivity type as the anode region and set with a higher impurity concentration than the anode region on a different portion on the main face of the anode region to the portion formed with the cathode region; forming wiring having one end portion connected to the contact region and another end portion extending over the p-n junction diode with a passivation film between the p-n junction diode and the wiring; and forming a channel stopper region under the wiring at a portion on the main face of the anode region between the contact region and the element isolation region, such that the channel stopper region has the same conductivity type as the cathode region and is formed in the same process as the process of forming the cathode region.