# US 2021/0280564 A1 · Semiconductor package having a high reliability

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- Number: US 2021/0280564 A1
- Document ID: US20210280564A1
- Status: Published application
- Kind: A1
- Application number: 17/329,036
- Filed: 2021-05-24
- Published: 2021-09-09
- Earliest claimed: 2016-02-22
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: JI-HWAN HWANG; SANG-SICK PARK; TAE-HONG MIN; GEOL NAM
- Web page: https://patentgrep.com/patent/US20210280564A1

## CPC

- H10W 90/00: Package configurations
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/072: {of bump connectors}
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/20: Configurations of stacked chips
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.

## Claims

### Claim 1

A semiconductor package, comprising:
a printed circuit board (PCB);
a first semiconductor device connected to the PCB by a first connection terminal;
a second semiconductor device connected to the first semiconductor device by a second connection terminal;
a first underfill fillet having a first height between the PCB and the first semiconductor device;
a second underfill fillet having a second height between the first semiconductor device and the second semiconductor device;
a third underfill fillet on the second semiconductor device;
a third semiconductor device on the third underfill fillet;
a fourth underfill fillet on the third semiconductor device;
a fourth semiconductor device on the fourth underfill fillet;
a thermal interface material (TIM) layer on the fourth semiconductor device; and
a heat dissipation member on the TIM layer;
wherein the first underfill fillet has a first protrusion from a side surface of the second semiconductor device and the second underfill fillet has a second protrusion from a side surface of the second semiconductor device, the first protrusion has a first dimension in a horizontal direction parallel to an upper surface of the PCB, the second protrusion has a second dimension in the horizontal direction, and the first dimension is greater than the second dimension,
wherein the first underfill fillet has a third protrusion from a side surface of the first semiconductor device and the second underfill fillet has a second protrusion from a side surface of the second semiconductor device, the third protrusion has a third dimension in a horizontal direction parallel to an upper surface of the PCB, the second protrusion has a second dimension in the horizontal direction, and the third dimension is greater than the second dimension, and
wherein an upper surface of the fourth semiconductor device is partially covered by the fourth underfill fillet.

### Claim 2

A semiconductor package, comprising:
a package substrate;
a first semiconductor device connected to the package substrate by a first connection terminal;
a second semiconductor device connected to the first semiconductor device by a second connection terminal;
a first underfill fillet having a first height between the package substrate and the first semiconductor device; and
a second underfill fillet having a second height between the first semiconductor device and the second semiconductor device,
wherein the first height is greater than the second height.

### Claim 3 (depends on 2)

The semiconductor package of claim 2, wherein each of the first height and the second height ranges from about 5 μm to about 100 μm.

### Claim 4 (depends on 2)

The semiconductor package of claim 2, wherein the first underfill fillet has a first protrusion from a side surface of the second semiconductor device and the second underfill fillet has a second protrusion from a side surface of the second semiconductor device,
the first protrusion has a first dimension in a horizontal direction parallel to an upper surface of the package substrate, the second protrusion has a second dimension in the horizontal direction, and the first dimension is greater than the second dimension.

### Claim 5 (depends on 2)

The semiconductor package of claim 2, wherein the first underfill fillet has a third protrusion from a side surface of the first semiconductor device and the second underfill fillet has a second protrusion from a side surface of the second semiconductor device,
the third protrusion has a third dimension in a horizontal direction parallel to an upper surface of the package substrate, the second protrusion has a second dimension in the horizontal direction, and the third dimension is greater than the second dimension.

### Claim 6 (depends on 2)

The semiconductor package of claim 2, further comprising:
a third underfill fillet on the second semiconductor device;
a third semiconductor device on the third underfill fillet;
a fourth underfill fillet on the third semiconductor device; and
a fourth semiconductor device on the fourth underfill fillet,
wherein the second underfill fillet has a height greater than that of the third underfill fillet, and the third underfill fillet has a height greater than that of the fourth underfill fillet.

### Claim 7 (depends on 6)

The semiconductor package of claim 6, wherein an upper surface of the fourth semiconductor device is not covered by the fourth underfill fillet.

### Claim 8 (depends on 6)

The semiconductor package of claim 6, wherein an upper surface of the fourth semiconductor device is partially covered by the fourth underfill fillet.

### Claim 9 (depends on 6)

The semiconductor package of claim 6, further comprising a heat dissipation member on the fourth semiconductor device.

### Claim 10 (depends on 9)

The semiconductor package of claim 9, further comprising a thermal interface material (TIM) layer between the heat dissipation member and the fourth semiconductor device.

### Claim 11 (depends on 2)

The semiconductor package of claim 2, wherein the package substrate is a printed circuit board (PCB).

### Claim 12 (depends on 2)

The semiconductor package of claim 2, further comprising a molding resin at least partially surrounding the first semiconductor device and the second semiconductor device.

### Claim 13

A semiconductor package, comprising:
a package substrate;
a first semiconductor device connected to the package substrate by a first connection terminal;
a second semiconductor device connected to the first semiconductor device by a second connection terminal;
a molding resin at least partially surrounding the first semiconductor device and the second semiconductor device;
a first underfill fillet between the package substrate and the first semiconductor device; and
a second underfill fillet between the first semiconductor device and the second semiconductor device,
wherein the first underfill fillet has a first protrusion from a side surface of the second semiconductor device and the second underfill fillet has a second protrusion from a side surface of the second semiconductor device,
the first protrusion has a first dimension in a horizontal direction parallel to an upper surface of the package substrate, the second protrusion has a second dimension in the horizontal direction, and the first dimension is greater than the second dimension.

### Claim 14 (depends on 13)

The semiconductor package of claim 13, wherein the package substrate is an interposer.

### Claim 15 (depends on 13)

The semiconductor package of claim 13, wherein the first underfill fillet has a first height ranging from about 5 μm to about 40 μm between the package substrate and the first semiconductor device,
the second underfill fillet has a second height of about 5 μm or greater and less than about 40 μm between the first semiconductor device and the second semiconductor device, and the first height is greater than the second height.

### Claim 16 (depends on 13)

The semiconductor package of claim 13, wherein the first underfill fillet has a third protrusion from a side surface of the first semiconductor device,
the third protrusion has a third dimension in the horizontal direction, and the third dimension is greater than the second dimension.

### Claim 17 (depends on 13)

The semiconductor package of claim 13, further comprising:
a third underfill fillet on the second semiconductor device;
a third semiconductor device on the third underfill fillet;
a fourth underfill fillet on the third semiconductor device; and
a fourth semiconductor device on the fourth underfill fillet,
wherein the second underfill fillet has a height greater than that of the third underfill fillet, and the third underfill fillet has a height greater than that of the fourth underfill fillet.

### Claim 18 (depends on 17)

The semiconductor package of claim 17, wherein the molding resin surrounds side surfaces of the third semiconductor device and the fourth semiconductor device, and an upper surface of the fourth semiconductor device is exposed from the molding resin.

### Claim 19 (depends on 18)

The semiconductor package of claim 18, wherein the upper surface of the fourth semiconductor device is coplanar with an upper surface of the molding resin.

### Claim 20 (depends on 13)

The semiconductor package of claim 13, wherein at least one of the first to the fourth underfill fillets includes a non-conductive film (NCF), a non-conductive paste (NCP), or an anisotropic conductive film (ACF).