# US 2021/0280561 A1 · Semiconductor device and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0280561 A1 - Document ID: US20210280561A1 - Status: Published application - Kind: A1 - Application number: 17/120,514 - Filed: 2020-12-14 - Published: 2021-09-09 - Earliest claimed: 2020-03-09 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Takashi WATANABE - Web page: https://patentgrep.com/patent/US20210280561A1 ## CPC - H10W 90/00: Package configurations - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 80/00: Direct bonding of chips, wafers or substrates - H10W 46/301: {for alignment} - H10W 72/01931: {using blanket deposition} - H10W 72/01953: {by etching} - H10W 72/01955: {by using masks} - H10W 72/0198: {batch processes} - H10W 72/921: {Structures or relative sizes of bond pads} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/985: {Alignment aids, e.g. alignment marks} - H10W 80/163: {using active alignment, e.g. detecting marks and correcting position} - H10W 80/312: {characterised by the direct bonding of electrically conductive pads} - H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers} - H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape - H10W 90/792: {between multiple chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device according to the present embodiment includes a first chip and a second chip. A first pad is disposed so as to be exposed from a first region on a first surface. A first mark is provided by a first pattern and is disposed so as to be exposed from a second region. The second chip includes a second substrate, a second wire, a second pad, and a second mark. The second wire is disposed on the second substrate. The second pad is disposed so as to be exposed from a third region on a second surface, and is electrically connected to the second wire and the first pad. The second mark is provided by a second pattern corresponding to the first pattern, is disposed so as to be exposed from a fourth region, and has a thinner thickness than the second pad. ## Claims ### Claim 1 A semiconductor device comprising: a first chip; and a second chip having a second surface on which the second chip is bonded to the first chip, the second surface being opposed to a first surface of the first chip, wherein the first chip includes a first substrate, a first wire that is disposed on the first substrate, a first pad that is disposed so as to be exposed from a first region on the first surface and that is electrically connected to the first wire, and a first mark that is provided by a first pattern and that is disposed so as to be exposed from a second region which is different from the first region, and the second chip includes a second substrate, a second wire that is disposed on the second substrate, a second pad that is disposed so as to be exposed from a third region on the second surface and that is electrically connected to the second wire and the first pad, and a second mark that is provided by a second pattern corresponding to the first pattern, that is disposed so as to be exposed from a fourth region which is different from the third region, and that has a thinner thickness than the second pad. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein a width of the second mark is narrower than a width of the second pad. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the second pad includes a first pad portion that is disposed so as to be exposed from the third region, and that has a thickness from the second surface equal to a thickness, of the second mark, from the second surface, and a second pad portion that is disposed below the first pad portion, and that is different in a width from the first pad portion. ### Claim 4 A manufacturing method of a semiconductor device, the method comprising: forming a first hole and a first trench of a first pattern, in a first region and a second region different from the first region on a first surface of a first wafer; forming, in the first hole, a first pad that is electrically connected to a first wire in the first wafer, and further, forming a first mark in the first trench; forming, in a third region and a fourth region different from the third region on a second surface of a second wafer, a second hole and a second trench of a second pattern corresponding to the first pattern, the second trench being shallower than the second hole; forming, in the second hole, a second pad that is electrically connected to a second wire in the second wafer, and further, forming a second mark in the second trench; bonding the first wafer and the second wafer together such that the first surface is opposed to the second surface; and detecting a positional deviation between the first pad and the second pad in accordance with the first mark and the second mark. ### Claim 5 (depends on 4) The manufacturing method of a semiconductor device according to claim 4, further comprising: detecting a positional deviation between the first pad and the second pad by detecting a position of the first mark and a position of the second mark from the second wafer side. ### Claim 6 (depends on 4) The manufacturing method of a semiconductor device according to claim 4, further comprising: forming, on the first surface, a mask having a thickness that is thinner in the third region than in the fourth region, prior to forming the second hole and the second trench; and forming the second hole, and further, forming the second trench. ### Claim 7 (depends on 5) The manufacturing method of a semiconductor device according to claim 5, further comprising: forming, on the first surface, a mask having a thickness that is thinner in the third region than in the fourth region, prior to forming the second hole and the second trench; and forming the second hole, and further, forming the second trench. ### Claim 8 (depends on 6) The manufacturing method of a semiconductor device according to claim 6, comprising forming the mask by lithography using a photomask in which a transmittance corresponding to the third region is higher than a transmittance corresponding to the fourth region, prior to forming the second hole and the second trench. ### Claim 9 (depends on 7) The manufacturing method of a semiconductor device according to claim 7, comprising forming the mask by lithography using a photomask in which a transmittance corresponding to the third region is higher than a transmittance corresponding to the fourth region, prior to forming the second hole and the second trench. ### Claim 10 (depends on 6) The manufacturing method of a semiconductor device according to claim 6, comprising forming the mask by lithography using a template that has a plurality of projections such that a projection corresponding to the third region is higher than a projection corresponding to the fourth region, prior to forming the second hole and the second trench. ### Claim 11 (depends on 7) The manufacturing method of a semiconductor device according to claim 7, comprising forming the mask by lithography using a template that has a plurality of projections such that a projection corresponding to the third region is higher than a projection corresponding to the fourth region, prior to forming the second hole and the second trench. ### Claim 12 (depends on 4) The manufacturing method of a semiconductor device according to claim 4, comprising forming the second hole, and further, forming the second trench that is shallower than the second hole by forming the second trench having a narrower width than the second hole. ### Claim 13 (depends on 5) The manufacturing method of a semiconductor device according to claim 5, comprising forming the second hole, and further, forming the second trench that is shallower than the second hole by forming the second trench having a narrower width than the second hole. ### Claim 14 (depends on 4) The manufacturing method of a semiconductor device according to claim 4, comprising: forming, in the third region, a third hole having a first width; and forming the second hole by forming, in the third region, a fourth hole having a second width different from the first width, and further, forming the second trench. ### Claim 15 (depends on 5) The manufacturing method of a semiconductor device according to claim 5, comprising: forming, in the third region, a third hole having a first width; and forming the second hole by forming, in the third region, a fourth hole having a second width different from the first width, and further, forming the second trench.