# US 2021/0280559 A1 · Semiconductor device including fractured semiconductor dies

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- Number: US 2021/0280559 A1
- Document ID: US20210280559A1
- Status: Published application
- Kind: A1
- Application number: 16/808,128
- Filed: 2020-03-03
- Published: 2021-09-09
- Earliest claimed: 2020-03-03
- Assignees: SanDisk Technologies LLC
- Applicants: Sandisk Technologies LLC
- Inventors: Daniel Linnen; Kirubakaran Periyannan; Jayavel Pachamuthu; Narendhiran CR; Jay Dholakia; Everett Lyons, IV; Hoang Huynh; Dat Dinh
- Web page: https://patentgrep.com/patent/US20210280559A1

## CPC

- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 90/00: Package configurations
- G11C 29/006: {at wafer scale level, i.e. wafer scale integration [WSI]}
- G11C 29/06: Acceleration testing
- H10W 20/493: {Fuses, i.e. interconnections changeable from conductive to non-conductive}
- H10W 72/90: Bond pads, in general
- G11C 2029/0403: {during or with feedback to manufacture}
- H10W 72/01: {Manufacture or treatment}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.

## Claims

### Claim 1

A semiconductor die, comprising:
a substrate;
die bond pads in the substrate, the die bond pads configured to transfer electrical signals to and from the semiconductor die; and
a memory cell array in the substrate, the memory cell array electrically coupled to the die bond pads, and the memory cell array divided into a plurality of blocks;
wherein the semiconductor die is fractured to a size smaller than an original size of the semiconductor die; and
wherein the semiconductor die is fractured at a block of the plurality of blocks at an edge of the semiconductor die.

### Claim 2

(canceled)

### Claim 3 (depends on 1)

The semiconductor die of claim 1, wherein the memory cell array is fractured upon fracturing the semiconductor die.

### Claim 4 (depends on 3)

The semiconductor die of claim 3, wherein the memory cell array comprises a plurality of blocks sequentially arranged along an axis of the semiconductor die, the memory cell array fractured in a plane perpendicular to the axis along which the blocks are arranged.

### Claim 5 (depends on 1)

The semiconductor die of claim 1, wherein the memory cell array comprises electrical traces electrically coupled to the die bond pads, wherein the electrical traces are fractured.

### Claim 6 (depends on 5)

The semiconductor die of claim 5, wherein the fractured electrical traces comprise bit lines in a memory cell array.

### Claim 7 (depends on 5)

The semiconductor die of claim 5, wherein a pair of electrical traces have been popped to clear an electrical short between the pair of electrical traces.

### Claim 8 (depends on 1)

The semiconductor die of claim 1, wherein the size of the fractured semiconductor die is customized based on a size of a semiconductor package including the semiconductor die.

### Claim 9 (depends on 1)

The semiconductor die of claim 1, wherein the size of the fractured semiconductor die is customized based on a size of a semiconductor package including the semiconductor die and a number of semiconductor die to be included in the package.

### Claim 10 (depends on 1)

The semiconductor die of claim 1, wherein the semiconductor die is chilled before the semiconductor die is fractured.

### Claim 11

A semiconductor device, comprising:
a first semiconductor die, comprising:
a first substrate,
a first group of die bond pads in the first substrate, the first group of die bond pads configured to transfer electrical signals to and from the first semiconductor die, and
first integrated circuits in the first substrate, the first integrated circuits electrically coupled to the first group of die bond pads;
wherein the first semiconductor die comprises fractured blocks at an edge of the first semiconductor die;
a second semiconductor die, comprising:
a second substrate,
a second group of die bond pads in the second substrate, the second group of die bond pads configured to transfer electrical signals to and from the second semiconductor die, and
second integrated circuits in the second substrate, the second integrated circuits electrically coupled to the second group of die bond pads;
wherein the second semiconductor die comprises a pair of popped traces at an edge of the second semiconductor die to clear an electrical short between the pair of popped traces.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the size of the second semiconductor die is customized based on a form factor of the semiconductor device.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein the second semiconductor die is a memory die and the second integrated circuits comprise a memory cell array.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the memory cell array is fractured upon fracturing the second semiconductor die.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, wherein the second integrated circuits comprise electrical traces electrically coupled to the second group of die bond pads, wherein the electrical traces are fractured.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the fractured electrical traces comprise bit lines in a memory cell array.

### Claim 17

(canceled)

### Claim 18 (depends on 11)

The semiconductor device of claim 11, wherein the second semiconductor die is chilled before the second semiconductor die is fractured.

### Claim 19 (depends on 11)

The semiconductor device of claim 11, wherein the first and second semiconductor dies are stacked on each other in an offset configuration to leave the first and second groups of bond pads exposed and available to receive a wire bond.

### Claim 20

A semiconductor die, comprising:
a substrate;
die bond pads, in the substrate, the die bond pads configured to transfer electrical signals to and from the semiconductor die;
a memory cell array in the substrate, the memory cell array comprising bit lines electrically coupled to the die bond pads;
wherein the semiconductor die is fractured to a size smaller than an original size of the semiconductor die; and
means for clearing electrical shorts between bit lines which contact each other upon fracturing of the semiconductor die.