# US 2021/0280557 A1 · Apparatuses and methods for coupling a plurality of semiconductor devices

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- Number: US 2021/0280557 A1
- Document ID: US20210280557A1
- Status: Published application
- Kind: A1
- Application number: 17/174,177
- Filed: 2021-02-11
- Published: 2021-09-09
- Earliest claimed: 2020-03-03
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Matthew B. Leslie; Timothy M. Hollis; Roy E. Greeff
- Web page: https://patentgrep.com/patent/US20210280557A1

## CPC

- H10W 90/00: Package configurations
- H10W 72/50: Bond wires
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Apparatuses and methods for coupling semiconductor devices are disclosed. Terminals (e.g., die pads) of a plurality of semiconductor devices may be coupled in a daisy chain manner through conductive structures that couple one or more terminals of a semiconductor device to two conductive bond pads. The conductive structures may be included in a redistribution layer (RDL) structure. The RDL structure may have a “U” shape in some embodiments of the disclosure. Each end of the “U” shape may be coupled to a respective one of the two conductive bond pads, and the terminal of the semiconductor device may be coupled to the RDL structure. The conductive bond pads of a semiconductor device may be coupled to conductive bond pads of other semiconductor devices by conductors (e.g., bond wires). As a result, the terminals of the semiconductor devices may be coupled in a daisy chain manner through the RDL structures, conductive bond pads, and conductors.

## Claims

### Claim 1

An apparatus, comprising:
a plurality of semiconductor devices including first, second, and third semiconductor devices, each of the plurality of semiconductor devices including a die pad coupled to at least one circuit of the respective semiconductor device, and further including a redistribution layer structure coupled to the die pad and further coupled to first and second bond pads, wherein the second bond pad of the first semiconductor device is coupled to the first bond pad of the second semiconductor device, and the second bond pad of the second semiconductor device is coupled to the first bond pad of the third semiconductor device.

### Claim 2 (depends on 1)

The apparatus of claim 1 wherein the plurality of semiconductor devices are included in a stack of semiconductor devices.

### Claim 3 (depends on 2)

The apparatus of claim 2 wherein the plurality of semiconductor devices are stacked in a staggered manner and an edge region of each of the semiconductor devices of the plurality is exposed, wherein the respective first and second bond pads are located at the edge regions of the plurality of semiconductor devices.

### Claim 4 (depends on 1)

The apparatus of claim 1 wherein the second bond pad of the first semiconductor device is coupled to the first bond pad of the second semiconductor device by a bond wire, and the second bond pad of the second semiconductor device is coupled to the first bond pad of the third semiconductor device by another bond wire.

### Claim 5 (depends on 1)

The apparatus of claim 1 wherein the redistribution layer structure of each of the plurality of semiconductor devices is U-shaped.

### Claim 6 (depends on 1)

The apparatus of claim 1 wherein the redistribution layer structure of each of the plurality of semiconductor devices includes a first portion extending between the die pad and the first bond pad and further includes a second portion extending between the die pad and the second bond pad.

### Claim 7 (depends on 6)

The apparatus of claim 6 wherein the redistribution layer structure of each of the plurality of semiconductor devices further includes a third portion coupled to the first and second portions and further coupled to the die pad.

### Claim 8 (depends on 1)

The apparatus of claim 1, further comprising:
an external circuit coupled to the first bond pad of the first semiconductor device; and
a substrate including conductive signal lines, wherein the plurality of semiconductor devices and the external circuit are attached to the substrate and the external circuit is coupled to the first bond pad of the first semiconductor device by the conductive signal lines.

### Claim 9 (depends on 1)

The apparatus of claim 1 wherein the respective die pad of each of the plurality of semiconductor devices is included in a peripheral circuit area that is located along a center region of the respective semiconductor device.

### Claim 10 (depends on 1)

The apparatus of claim 1 wherein the respective die pads of each of the plurality of semiconductor devices are coupled together in a daisy chain through the bond pads and redistribution layer structures.

### Claim 11

A multi-die device, comprising:
a substrate including a conductive signal line;
a stack of semiconductor devices attached to the substrate, each of the semiconductor devices of the stack including a terminal and a redistribution layer structure coupled to the terminal, and wherein the terminals of the semiconductor devices of the stack are coupled together in a daisy chain manner through the redistribution layer structures; and
a circuit attached to the substrate and coupled to a first semiconductor device of the stack of semiconductor devices by the conductive signal line.

### Claim 12 (depends on 11)

The multi-die device of claim 11 wherein each of the semiconductor devices further includes first and second bond pads, wherein the first bond pad is coupled to a first portion of the redistribution layer structure and the second bond pad is coupled to a second portion of the redistribution layer structure.

### Claim 13 (depends on 12)

The multi-die device of claim 12 wherein the first and second bond pads of each semiconductor device are located at an edge region and the terminal is included in a peripheral circuit area that is located along a center region of the respective semiconductor device.

### Claim 14 (depends on 12)

The multi-die device of claim 12 wherein the one of the first and second bond pads of a semiconductor device of the stack is coupled to one of the first and second bond pads of another semiconductor device of the stack by a bond wire.

### Claim 15 (depends on 12)

The multi-die device of claim 12 wherein the first portion includes a first conductive structure formed from a conductive layer different than the first bond pad and the terminal and wherein the second portion includes a second conductive structure formed from the same conductive layer.

### Claim 16 (depends on 11)

The multi-die device of claim 11 wherein the circuit attached to the substrate comprises a register clock driver (RCD) circuit.

### Claim 17 (depends on 11)

The multi-die device of claim 11 wherein the terminal comprises a data terminal or a command address terminal.

### Claim 18 (depends on 11)

The multi-die device of claim 11 wherein the redistribution layer structure comprises a U-shaped redistribution layer structure.

### Claim 19

An apparatus, comprising:
a memory army configured to store data;
a terminal;
an input/output circuit configured to receive data from the memory array and provide read data and receive write data to be stored in the memory array;
a command and address input circuit configured to receive command and address signals;
first and second bond pads; and
a U-shaped conductive structure coupled to the terminal and including a first portion extending between and coupled to the terminal and the first bond pad and further including a second portion extending between and coupled to the terminal and the second bond pad.

### Claim 20 (depends on 19)

The apparatus of claim 19 wherein the input/output circuit is coupled to the terminal and configured to provide the read data to the terminal and configured to receive the write data from the terminal.

### Claim 21 (depends on 19)

The apparatus of claim 19 wherein the command and address input circuit is coupled to the terminal and configured to receive command and address signals from the terminal.

### Claim 22 (depends on 19)

The apparatus of claim 19 wherein the U-shaped conductive structure further includes a third portion coupled to the first and second portions and further coupled to the terminal.

### Claim 23 (depends on 19)

The apparatus of claim 19 wherein the terminal comprises a die pad included in a peripheral circuit area.

### Claim 24 (depends on 19)

The apparatus of claim 19 wherein the first and second bond pads are located at an edge and the terminal is located in an area along a center region disposed between memory cell array areas of the memory array.

### Claim 25

A method, comprising:
coupling a bond bad of a first semiconductor device to a first U-shaped conductive structure;
coupling a bond bad of a second semiconductor device to a second U-shaped conductive structure;
coupling a bond bad of a third semiconductor device to a third U-shaped conductive structure;
coupling a second portion of the first U-shaped conductive structure to a first portion of the second U-shaped conductive structure; and
coupling a second portion of the second U-shaped conductive structure to a first portion of the third U-shaped conductive structure,
wherein a first portion of the first U-shaped conductive structure is coupled to a circuit and wherein a second portion of the third U-shaped conductive structure is coupled to a fourth semiconductor device.