# US 2021/0280554 A1 · Semiconductor apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0280554 A1 - Document ID: US20210280554A1 - Status: Published application - Kind: A1 - Application number: 17/064,731 - Filed: 2020-10-07 - Published: 2021-09-09 - Earliest claimed: 2020-03-06 - Assignees: Mitsubishi Electric Corporation - Applicants: Mitsubishi Electric Corporation - Inventors: Koichi TOKUBO - Web page: https://patentgrep.com/patent/US20210280554A1 ## CPC - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 90/811: {Multiple chips on leadframes} - H10W 40/251: {Organics} - H10W 40/778: {in encapsulations} - H10W 70/458: {of insulating layers on leadframes} - H10W 70/465: {Bumps or wires} - H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00} - H10W 70/417: {Bonding materials between chips and die pads} - H10W 72/07331: {Connecting techniques} - H10W 72/07336: {Soldering or alloying} - H10W 72/07533: {Ultrasonic bonding, e.g. thermosonic bonding} - H10W 72/07552: {changes in structures or sizes} - H10W 72/07553: {changes in shapes} - H10W 72/07555: {changes in materials} - H10W 72/07653: {changes in shapes} - H10W 72/325: {Die-attach connectors having a filler embedded in a matrix} - H10W 72/352: {comprising metals or metalloids, e.g. solders} - H10W 72/527: {Multiple bond wires having different sizes} - H10W 72/531: {Shapes of wire connectors} - H10W 72/5438: {the bond wires having multiple connections on the same bond pad} - H10W 72/5453: {connecting between multiple bond pads on a chip, e.g. daisy chain} - H10W 72/551: {Materials of bond wires} - H10W 72/552: {comprising metals or metalloids, e.g. silver} - H10W 72/5522: {comprising gold [Au]} - H10W 72/5524: {comprising aluminium [Al]} - H10W 72/5525: {comprising copper [Cu]} - H10W 72/59: Bond pads specially adapted therefor - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/753: {between laterally-adjacent chips} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor apparatus includes: a metal plate; a semiconductor device mounted on the metal plate; an external terminal electrically connected to the semiconductor device or the metal plate; a metal wire wire-bonded to the semiconductor device, the metal plate or the external terminal; and a package covering and resin-sealing the semiconductor device, the metal plate and the metal wire, wherein the metal wire is bonded to a top-layer electrode of the semiconductor device at a first bond and a second bond, and the metal wire includes a low loop that is positioned between the first bond and the second bond, is adjacent to at least one of the first bond and the second bond and is not in contact with the top-layer electrode. ## Claims ### Claim 1 A semiconductor apparatus comprising: a metal plate; a semiconductor device mounted on the metal plate; an external terminal electrically connected to the semiconductor device or the metal plate; a metal wire wire-bonded to the semiconductor device, the metal plate or the external terminal; and a package covering and resin-sealing the semiconductor device, the metal plate and the metal wire, wherein the metal wire is bonded to a top-layer electrode of the semiconductor device at a first bond and a second bond, and the metal wire includes a low loop that is positioned between the first bond and the second bond, is adjacent to at least one of the first bond and the second bond and is not in contact with the top-layer electrode. ### Claim 2 (depends on 1) The semiconductor apparatus according to claim 1, wherein the metal wire is linearly in contact with the top-layer electrode between the low loop adjacent to the first bond and the low loop adjacent to the second bond. ### Claim 3 (depends on 1) The semiconductor apparatus according to claim 1, wherein the metal wire is bonded to multiple points of the top-layer electrode between the low loop adjacent to the first bond and the low loop adjacent to the second bond. ### Claim 4 (depends on 2) The semiconductor apparatus according to claim 2, wherein the metal wire is bonded to multiple points of the top-layer electrode between the low loop adjacent to the first bond and the low loop adjacent to the second bond. ### Claim 5 (depends on 1) The semiconductor apparatus according to claim 1, wherein the metal wire is separated from the top-layer electrode by a certain distance and is not in contact with the top-layer electrode between the low loop adjacent to the first bond and the low loop adjacent to the second bond. ### Claim 6 (depends on 1) The semiconductor apparatus according to claim 1, wherein a height of the low loop of the metal wire with respect to the top-layer electrode is less than twice a diameter of the metal wire. ### Claim 7 (depends on 2) The semiconductor apparatus according to claim 2, wherein a height of the low loop of the metal wire with respect to the top-layer electrode is less than twice a diameter of the metal wire. ### Claim 8 (depends on 3) The semiconductor apparatus according to claim 3, wherein a height of the low loop of the metal wire with respect to the top-layer electrode is less than twice a diameter of the metal wire. ### Claim 9 (depends on 4) The semiconductor apparatus according to claim 4, wherein a height of the low loop of the metal wire with respect to the top-layer electrode is less than twice a diameter of the metal wire. ### Claim 10 (depends on 5) The semiconductor apparatus according to claim 5, wherein a height of the low loop of the metal wire with respect to the top-layer electrode is less than twice a diameter of the metal wire. ### Claim 11 (depends on 1) The semiconductor apparatus according to claim 1, wherein the metal wire is made of a conductive metal containing any of Al, Cu, and Ag. ### Claim 12 (depends on 2) The semiconductor apparatus according to claim 2, wherein the metal wire is made of a conductive metal containing any of Al, Cu, and Ag. ### Claim 13 (depends on 3) The semiconductor apparatus according to claim 3, wherein the metal wire is made of a conductive metal containing any of Al, Cu, and Ag. ### Claim 14 (depends on 4) The semiconductor apparatus according to claim 4, wherein the metal wire is made of a conductive metal containing any of Al, Cu, and Ag. ### Claim 15 (depends on 5) The semiconductor apparatus according to claim 5, wherein the metal wire is made of a conductive metal containing any of Al, Cu, and Ag. ### Claim 16 (depends on 6) The semiconductor apparatus according to claim 6, wherein the metal wire is made of a conductive metal containing any of Al, Cu, and Ag. ### Claim 17 (depends on 7) The semiconductor apparatus according to claim 7, wherein the metal wire is made of a conductive metal containing any of Al, Cu, and Ag. ### Claim 18 (depends on 8) The semiconductor apparatus according to claim 8, wherein the metal wire is made of a conductive metal containing any of Al, Cu, and Ag. ### Claim 19 (depends on 9) The semiconductor apparatus according to claim 9, wherein the metal wire is made of a conductive metal containing any of Al, Cu, and Ag. ### Claim 20 (depends on 10) The semiconductor apparatus according to claim 10, wherein the metal wire is made of a conductive metal containing any of Al, Cu, and Ag.