# US 2021/0280547 A1 · Zinc-cobalt barrier for interface in solder bond applications

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2021/0280547 A1
- Document ID: US20210280547A1
- Status: Published application
- Kind: A1
- Application number: 17/323,939
- Filed: 2021-05-18
- Published: 2021-09-09
- Earliest claimed: 2019-10-22
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Nazila Dadvand; Christopher Daniel Manack; Salvatore Frank Pavone
- Web page: https://patentgrep.com/patent/US20210280547A1

## CPC

- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- B23K 1/0016: {Soldering of electronic components}
- B23K 1/008: Soldering within a furnace (B23K1/012 takes precedence)
- B23K 1/19: taking account of the properties of the materials to be soldered
- B23K 3/0638: {for viscous material feeding, e.g. solder paste feeding (B23K3/0623 takes precedence)}
- B23K 3/0669: {with dipping means}
- B23K 3/08: Auxiliary devices therefor
- B23K 26/0006: {taking account of the properties of the material involved (B23K26/32, B23K26/40 take precedence)}
- B23K 26/34: Laser welding for purposes other than joining
- B33Y 80/00: Products made by additive manufacturing
- C25D 5/022: {using masking means}
- C25D 5/12: at least one layer being of nickel or chromium
- C25D 5/18: Electroplating using modulated, pulsed or reversing current
- C25D 5/50: by heat-treatment
- C25D 7/123: {Semiconductors first coated with a seed layer or a conductive layer}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/415: {Leadframe inner leads serving as die pads}
- H10W 70/457: {of metallic layers on leadframes}
- H10W 70/66: Conductive materials thereof
- B23K 35/02: characterised by mechanical features, e.g. shape
- B23K 35/025: {Pastes, creams or slurries}
- B23K 35/262: {Sn as the principal constituent}
- B23K 2101/36: Electric or electronic devices
- B23K 2101/42: Printed circuits
- B23K 2103/12: Copper or alloys thereof
- B33Y 40/20: Post-treatment, e.g. curing, coating or polishing
- C25D 3/12: of nickel or cobalt
- C25D 3/22: of zinc
- C25D 3/38: of copper
- H10P 14/47: Electrolytic deposition, i.e. electroplating; Electroless plating
- H10W 20/038: {covering conductive structures (H10W20/037 takes precedence)}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01255: {by using masks}
- H10W 72/01257: {by reflowing}
- H10W 72/01261: {Chemical or physical modification, e.g. by sintering or anodisation (patterning H10W72/01251)}
- H10W 72/019: {of bond pads}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07253: {changes in shapes}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B23K: SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B33Y: ADDITIVE MANUFACTURING, i.e. MANUFACTURING OF THREE-DIMENSIONAL [3D] OBJECTS BY ADDITIVE DEPOSITION, ADDITIVE AGGLOMERATION OR ADDITIVE LAYERING, e.g. BY 3D PRINTING, STEREOLITHOGRAPHY OR SELECTIVE LASER SINTERING
- C25D: PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A microelectronic device has bump bond structures on input/output (I/O) pads. The bump bond structures include copper-containing pillars, a barrier layer including cobalt and zinc on the copper-containing pillars, and tin-containing solder on the barrier layer. The barrier layer includes 0.1 weight percent to 50 weight percent cobalt and an amount of zinc equivalent to a layer of pure zinc 0.05 microns to 0.5 microns thick. A lead frame has a copper-containing member with a similar barrier layer in an area for a solder joint. Methods of forming the microelectronic device are disclosed.

## Claims

### Claim 1

A method of forming a microelectronic device, comprising:
providing a substrate having an input/output (I/O) pad;
forming a copper-containing structure an input/output (I/O) pad of a substrate;
forming a layer on the copper-containing structure, wherein the layer includes 0.1 weight percent to 50 weight percent cobalt, and wherein the layer includes an amount of zinc equivalent to a layer of pure zinc 0.05 microns to 0.5 microns thick; and
forming solder on the layer, so that the solder includes tin.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the layer includes:
electroplating a cobalt-containing sublayer on the copper-containing structure, so that a weight percentage of cobalt in the cobalt-containing sublayer is higher than a weight percentage of zinc in the cobalt-containing sublayer; and
electroplating a zinc-containing sublayer on the cobalt-containing sublayer, so that the zinc-containing sublayer includes an amount of zinc equivalent to a layer of pure zinc 0.05 microns to 0.5 microns thick.

### Claim 3 (depends on 2)

The method of claim 2, further including heating the cobalt-containing sublayer and the zinc-containing sublayer to 200° C. to 270° C. to form the layer.

### Claim 4 (depends on 2)

The method of claim 2, wherein forming the layer further includes electroplating nickel.

### Claim 5 (depends on 1)

The method of claim 1, wherein forming the layer includes exposing the copper-containing structure to an electroplating bath, the electroplating bath including cobalt and zinc, and electroplating the cobalt and the zinc concurrently from the electroplating bath onto the copper structure.

### Claim 6 (depends on 5)

The method of claim 5, wherein electroplating the cobalt and the zinc is performed using a reverse pulse plating process.

### Claim 7 (depends on 5)

The method of claim 5, wherein the electroplating bath includes nickel, and forming the layer includes electroplating nickel concurrently with the cobalt and the zinc.

### Claim 8 (depends on 1)

The method of claim 1, wherein forming the layer includes an additive process which dispenses material onto the copper pillars, the material including cobalt and zinc.

### Claim 9 (depends on 1)

The method of claim 1, wherein the layer is a barrier layer.

### Claim 10

A method of forming a microelectronic device, comprising:
providing a substrate having an input/output (I/O) pad;
forming a copper-containing pillar, so that the copper-containing pillar includes at least 90 weight percent copper;
forming a barrier layer on the copper-containing pillar, so that the barrier layer includes 0.1 weight percent to 50 weight percent cobalt, and so that the barrier layer includes an amount of zinc equivalent to a layer of pure zinc 0.05 microns to 0.5 microns thick; and
forming solder on the barrier layer, so that the solder includes tin.

### Claim 11 (depends on 10)

The method of claim 10, wherein forming the barrier layer includes:
electroplating a cobalt-containing sublayer on the copper-containing pillar, so that a weight percentage of cobalt in the cobalt-containing sublayer is higher than a weight percentage of zinc in the cobalt-containing sublayer; and
electroplating a zinc-containing sublayer on the cobalt-containing sublayer, so that the zinc-containing sublayer includes an amount of zinc equivalent to a layer of pure zinc 0.05 microns to 0.5 microns thick.

### Claim 12 (depends on 11)

The method of claim 11, further including heating the cobalt-containing sublayer and the zinc-containing sublayer to 200° C. to 270° C. to form the barrier layer.

### Claim 13 (depends on 11)

The method of claim 11, wherein forming the barrier layer further includes electroplating nickel.

### Claim 14 (depends on 10)

The method of claim 10, wherein forming the barrier layer includes exposing the copper-containing pillar to a barrier electroplating bath, the barrier electroplating bath including cobalt and zinc, and electroplating the cobalt and the zinc concurrently from the barrier electroplating bath onto the copper pillar.

### Claim 15 (depends on 14)

The method of claim 14, wherein electroplating the cobalt and the zinc is performed using a reverse pulse plating process.

### Claim 16 (depends on 14)

The method of claim 14, wherein the barrier electroplating bath includes nickel, and forming the barrier layer includes electroplating nickel concurrently with the cobalt and the zinc.

### Claim 17 (depends on 10)

The method of claim 10, wherein forming the barrier layer includes an additive process which dispenses barrier material onto the copper pillars, the barrier material including cobalt and zinc.