# US 2021/0280546 A1 · Stacked semiconductor device and multiple chips used therein > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0280546 A1 - Document ID: US20210280546A1 - Status: Published application - Kind: A1 - Application number: 17/255,814 - Filed: 2019-11-06 - Published: 2021-09-09 - Earliest claimed: 2018-11-21 - Assignees: Tohoku-Microtec Co., Ltd. - Applicants: Tohoku-Microtec Co., Ltd. - Inventors: Makoto MOTOYOSHI - Web page: https://patentgrep.com/patent/US20210280546A1 ## CPC - H10W 90/00: Package configurations - H10W 72/00: Interconnections or connectors in packages - H10W 72/071: {Connecting or disconnecting} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 72/072: {of bump connectors} - H10W 72/234: {Cross-sectional shape, i.e. in side view} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A stacked semiconductor device encompasses a mother-substrate, rectangular chips mounted on the mother-substrate, and bump-connecting mechanisms connecting the mother-substrate and the chips by a non-provisional joint-process with a height lower than the height of a provisional joint-process jointing the mother-substrate and the chips. The mother-substrate has unit elements arranged in each of unit-element areas assigned to a first lattice defined on a first main surface of the mother-substrate, the first main surface is divided into chip-mounting areas along a second lattice having a smaller number of meshes than the first lattice. The bump-connecting mechanisms are arranged along a third lattice corresponding to the arrangement of the unit elements, and transmit signals from the unit elements independently to each of the circuits merged in the chips. After the provisional joint-process, the bump-connecting mechanisms can be separated into substrate-side and chip-side connection-elements. ## Claims ### Claim 1 A stacked semiconductor device comprising: a mother-substrate having a first main surface and a second main surface facing to the first main surface, and a plurality of unit elements arranged in each of unit-element areas assigned to a first lattice defined on the first main surface, the first main surface is divided into a plurality of chip-mounting areas along a second lattice having a smaller number of meshes than the first lattice; a plurality of rectangular chips mounted on the first main surface side, each of the chips facing to corresponding site of the chip-mounting areas, respectively; and a plurality of bump-connecting mechanisms connecting the mother-substrate and each of the chips by a non-provisional joint-process with a height lower than the height of a provisional joint-process jointing the mother-substrate and the plurality of the chips, being arranged along a third lattice corresponding to the arrangement of the plurality of the unit elements, configured to transmit signals from the plurality of the unit elements independently to each of the circuits merged in the plurality of the chips, wherein, after the provisional joint-process, the plurality of the bump-connecting mechanisms can be separated into a plurality of substrate-side connection-elements and a plurality of chip-side connection-elements, each of which corresponds to the plurality of the substrate-side connection-elements. ### Claim 2 (depends on 1) The stacked semiconductor device of claim 1, wherein the plurality of substrate-side connection-elements comprises a plurality of first lands arranged along the third lattice, configured to deliver signals from each of the unit-elements, respectively; and the plurality of chip-side connection-elements comprises a plurality of second lands arranged on a chip surface of each of the chips, the chip surface is facing to the first main surface, along the third lattice, configured to feed the signals to each of the circuits merged in the plurality of the chips, respectively. ### Claim 3 (depends on 2) The stacked semiconductor device of claim 2, wherein each of the plurality of the substrate-side connection-elements further comprises a first bump having: a bottom portion in contact with the first land, and a cylindrical sidewall-portion connected to the outer periphery of the bottom portion. ### Claim 4 (depends on 3) The stacked semiconductor device of claim 3, wherein each of the plurality of the chip-side connection-elements further comprises a second bump whose bottom surface is in contact with the second land, configured to metallurgically joint to a part of the sidewall-portion of the first bump, under the provisional joint-process. ### Claim 5 (depends on 3) The stacked semiconductor device of claim 3, wherein the second bump includes a cone having a conical shape whose bottom surface is in contact with the second land, and an upper edge of the sidewall-portion of the first bump is metallurgically jointed to a part of the conical surface of the cone, under the provisional joint-process. ### Claim 6 (depends on 4) The stacked semiconductor device of claim 4, wherein the second bump includes a bottom portion in contact with the second land, and a tubular sidewall-portion connected to an outer periphery of the bottom portion, wherein an upper edge of the sidewall-portion of the first bump is deformed to cut recesses, as the sidewall-portion of the second bump bites the upper edge of the sidewall-portion of the first bump, under the provisional joint-process. ### Claim 7 A combination of a plurality of chips, each of the chips is supposed to be mounted respectively on corresponding chip-mounting areas defined on a mother-substrate, the mother-substrate having a first main surface and a second main surface facing to the first main surface, and a plurality of unit elements are arranged in each of unit-element areas assigned to a first lattice defined on the first main surface, the first main surface is divided into the chip-mounting areas along a second lattice having a smaller number of meshes than the first lattice, the mother-substrate has a plurality of substrate-side connection-elements for delivering each of signals from the plurality of the unit elements, each of the substrate-side connection-elements is assigned to a third lattice defined on the first main surface so that third lattice corresponds to an array of the unit elements, the number of chips is larger than the number of meshes of the second lattice, each of the chips comprising: a plurality of chip-side connection-elements feeding the signals to a circuit merged in each of the chips, arranged along the third lattice on a chip surface of each of the chips, the chip surface is facing to the first main surface, wherein, the mother-substrate and the plurality of the chips are provisionally jointed, and signals from the plurality of the unit elements are independently transmitted to circuits merged in the plurality of the chips to inspect normal operations of the chips, in a case of a defect determination such that a specific chip is determined to be defective, the specific chip is removed from the chip mounting area, and a new chip is provisionally jointed again, when all of the chips mounted on the mother-substrate is determined to be normal, the mother-substrate and the plurality of the chips are coupled to each other, by a non-provisional joint-process of compressing a height of the chip-side connection-element, decreasing the height lower than the value of the provisional joint-process. ### Claim 8 (depends on 7) The combination of claim 7, wherein the plurality of substrate-side connection-elements comprises a plurality of first lands arranged along the third lattice and a plurality of first bumps, each having a bottom portion in contact with the first land, and a cylindrical sidewall-portion connected to the outer periphery of the bottom portion, configured to deliver signals from each of the unit-elements, respectively; and the plurality of chip-side connection-elements comprises a plurality of second lands arranged on a chip surface of each of the chips, respectively, the chip surface is facing to the first main surface, along the third lattice, and a plurality of second bumps whose bottom surfaces are in contact with the second lands, respectively, configured to metallurgically joint respectively to corresponding parts of the sidewall-portions of the first bumps, under the provisional joint-process, each of second lands is configured to feed the signals to each of the circuits merged in the plurality of the chips, respectively. ### Claim 9 (depends on 8) The combination of claim 8, wherein each of the second bumps includes a cone having a conical shape whose bottom surface is in contact with the corresponding second land in the plurality of the second lands, and an upper edge of the sidewall-portion of the first bump is metallurgically jointed to a part of the conical surface of the cone, under the provisional joint-process. ### Claim 10 (depends on 8) The combination of claim 8, wherein each of the second bumps includes a bottom portion in contact with the corresponding second land in the plurality of the second lands, and a tubular sidewall-portion connected to an outer periphery of the bottom portion, wherein an upper edge of the sidewall-portion of each of the first bumps is deformed to cut recesses, as each of the sidewall-portions of the second bumps bites the upper edge of the corresponding sidewall-portion of the first bump, under the provisional joint-process.