# US 2021/0280522 A1 · Multi-molding method for fan-out stacked semiconductor package

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- Number: US 2021/0280522 A1
- Document ID: US20210280522A1
- Status: Published application
- Kind: A1
- Application number: 16/890,859
- Filed: 2020-06-02
- Published: 2021-09-09
- Earliest claimed: 2020-03-04
- Assignees: Powertech Technology Inc.
- Applicants: Powertech Technology Inc.
- Inventors: Sheng-Jie LIU
- Web page: https://patentgrep.com/patent/US20210280522A1

## CPC

- H10W 70/614: {the multiple chips being integrally enclosed}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/01: Manufacture or treatment
- H10W 74/016: {using moulds}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/00: Package configurations
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/635: {Through-vias}
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A multi-molding method for fan-out stacked semiconductor package is disclosed. Two molding chambers with different sizes are provided. Multiple first packages made in front-end packaging process are placed in a first molding chamber with smaller size to form a first molding compound. After then, multiple second packages made in back-end are placed in a second molding chamber with larger size to form a second molding compound. The second molding compound encapsulates the first molding compound. Therefore, the multi-molding method of the present invention is adapted to be used in fan-out panel level package process without an expensive compression mold tape.

## Claims

### Claim 1

A multi-molding method for fan-out stacked semiconductor package, comprising:
(a) providing a carrier for a fan-out semiconductor level package;
(b) forming multiple first packages on the carrier;
(c) placing the multiple first packages in a first molding chamber to form a first molding compound encapsulating the first packages;
(d) forming a first redistribution layer on an exposed surface of the first molding compound;
(e) forming multiple second packages on the first redistribution layer;
(f) placing the first molding compound, the first redistribution layer and the second packages in a second molding chamber to form a second molding compound encapsulating the first molding compound and the first redistribution layer; wherein the second molding chamber is larger than the first molding chamber;
(g) removing the carrier; and
(h) executing a singulation process to produce multiple fan-out stacked semiconductor packages.

### Claim 2 (depends on 1)

The multi-molding method as claimed in claim 1, wherein a surface of the first molding compound corresponding to the carrier is exposed and multiple outer connections are formed on the exposed surface of the first molding compound after removing the carrier in the step (g).

### Claim 3 (depends on 1)

The multi-molding method as claimed in claim 1, wherein the step (b) further comprising:
(b1) forming a second redistribution layer on the carrier;
(b2) adhering multiple rear faces of multiple first chips on the second redistribution layer, wherein multiple bumps are respectively formed on multiple pads of an active face of each of the first chips; and
(b3) forming multiple metal pillars on the second redistribution layer and around each of the first chips; wherein the metal pillars are electrically connected to the second redistribution layer, multiple free ends of the metal pillars and the bumps are coplanar.

### Claim 4 (depends on 2)

The multi-molding method as claimed in claim 2, wherein the step (b) further comprising:
(b1) forming a second redistribution layer on the carrier;
(b2) adhering multiple rear faces of multiple first chips on the second redistribution layer, wherein multiple bumps are respectively formed on multiple pads of an active face of each of the first chips; and
(b3) forming multiple metal pillars on the second redistribution layer and around each of the first chips; wherein the metal pillars are electrically connected to the second redistribution layer, multiple free ends of the metal pillars and the bumps are coplanar.

### Claim 5 (depends on 3)

The multi-molding method as claimed in claim 3, wherein the exposed surface of the first molding compound and the free ends of the metal pillars and the bumps are coplanar in the step (c).

### Claim 6 (depends on 4)

The multi-molding method as claimed in claim 4, wherein the exposed surface of the first molding compound and the free ends of the metal pillars and the bumps are coplanar in the step (c).

### Claim 7 (depends on 5)

The multi-molding method as claimed in claim 5, wherein the first redistribution layer is electrically connected to the metal pillars and the bumps in the step (d).

### Claim 8 (depends on 6)

The multi-molding method as claimed in claim 6, wherein the first redistribution layer is electrically connected to the metal pillars and the bumps in the step (d).

### Claim 9 (depends on 7)

The multi-molding method as claimed in claim 7, wherein each of the second packages having an active face of the at least one second chip disposed towards the first redistribution layer and electrically connected to the first redistribution layer in the step (e).

### Claim 10 (depends on 8)

The multi-molding method as claimed in claim 8, wherein each of the second packages having an active face of the at least one second chip disposed towards the first redistribution layer and electrically connected to the first redistribution layer in the step (e).

### Claim 11 (depends on 5)

The multi-molding method as claimed in claim 5, wherein an underfill is filled between an active face of the at least one second chip of each of the second packages and the first redistribution layer in the step (e).

### Claim 12 (depends on 6)

The multi-molding method as claimed in claim 6, wherein an underfill is filled between an active face of the at least one second chip of each of the second packages and the first redistribution layer in the step (e).

### Claim 13 (depends on 7)

The multi-molding method as claimed in claim 7, wherein the second molding compound further encapsulates the underfill in the step (f).

### Claim 14 (depends on 8)

The multi-molding method as claimed in claim 8, wherein the second molding compound further encapsulates the underfill in the step (f).

### Claim 15 (depends on 3)

The multi-molding method as claimed in claim 3, wherein each of the outer connections is a solder ball in the step (f).

### Claim 16 (depends on 4)

The multi-molding method as claimed in claim 4, wherein each of the outer connections is a solder ball in the step (f).

### Claim 17 (depends on 1)

The multi-molding method as claimed in claim 1, wherein:
a width of the carrier in the step (a) is larger than or equal to 500 mm;
a width of the second molding chamber is larger than or equal to 500 mm; and
a width of the first molding chamber is smaller than 500 mm.