# US 2021/0280499 A1 · 3d semiconductor device with isolation layers

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- Number: US 2021/0280499 A1
- Document ID: US20210280499A1
- Status: Published application
- Kind: A1
- Application number: 17/313,986
- Filed: 2021-05-06
- Published: 2021-09-09
- Earliest claimed: 2012-04-09
- Assignees: Monolithic 3D Inc.
- Applicants: Monolithic 3D Inc.
- Inventors: Zvi Or-Bach; Deepak C. Sekar; Brian Cronquist
- Web page: https://patentgrep.com/patent/US20210280499A1

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells}
- H10B 12/50: {Peripheral circuit region structures}
- H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 41/40: characterised by the peripheral circuit region
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/40: characterised by the peripheral circuit region
- H10D 10/051: {of vertical BJTs (of heterojunction BJTs H10D10/021; of Schottky BJTs H10D10/031; of thin film BJTs H10D10/041)}
- H10D 10/40: Vertical BJTs {(Vertical Heterojunction BJTs H10D10/821)}
- H10D 30/026: {having laterally-coplanar source and drain regions, a gate at the sides of the bulk channel, and both horizontal and vertical current flow (of LDMOS H10D30/0289)}
- H10D 30/0289: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/0512: {of FETs having PN homojunction gates}
- H10D 30/711: {having floating bodies}
- H10D 30/83: FETs having PN junction gate electrodes
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/343: {Gate regions of field-effect devices having PN junction gates}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/834: {comprising FinFETs}
- H10D 84/907: {CMOS gate arrays}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 89/10: Integrated device layouts
- H10W 20/021: {of interconnections within wafers or substrates}
- H10W 40/00: Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60)
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 72/00: Interconnections or connectors in packages
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/845: {the switching components being connected to a common vertical conductor}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/401: {Combinations of FETs or IGBTs with BJTs}
- H10W 46/301: {for alignment}
- H10W 46/501: {for use before dicing}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A 3D semiconductor device, the device including: a first level including single crystal first transistors, and a first metal layer, where the first level is overlaid by a first isolation layer; a second level including second transistors, where the first isolation layer is overlaid by the second level, and where the second level is overlaid by a second isolation layer; a third level including single crystal third transistors, where the second isolation layer is overlaid by the third level, where the third level is overlaid by a third isolation layer, where the third level is bonded to the second isolation layer, and where the bonded includes at least one oxide to oxide bond.

## Claims

### Claim 1

A 3D semiconductor device, the device comprising:
a first level comprising single crystal first transistors, and a first metal layer,
wherein said first level is overlaid by a first isolation layer;
a second level comprising second transistors,
wherein said first isolation layer is overlaid by said second level, and
wherein said second level is overlaid by a second isolation layer;
a third level comprising single crystal third transistors,
wherein said second isolation layer is overlaid by said third level,
wherein said third level is overlaid by a third isolation layer,
wherein said third level is bonded to said second isolation layer, and
wherein said bonded comprises at least one oxide to oxide bond.

### Claim 2 (depends on 1)

The device according to claim 1,
wherein said first isolation layer and said second isolation layer are separated by a distance of less than four microns and greater than 10 nm.

### Claim 3 (depends on 1)

The device according to claim 1, further comprising:
a connective path between said third transistors and said second transistors,
wherein said connective path comprises a via through said second isolation layer, and
wherein said via has a diameter of less than 400 nm and greater than 5 nm.

### Claim 4 (depends on 1)

The device according to claim 1, further comprising:
a heat removal path from said second transistors to an external surface of said device.

### Claim 5 (depends on 1)

The device according to claim 1, further comprising:
a power delivery path to said second transistors,
wherein at least a portion of said power delivery path is underneath at least one of said second transistors.

### Claim 6 (depends on 1)

The device according to claim 1,
wherein said first level comprises a second metal layer overlaying said first metal layer, and
wherein said second metal layer is disposed underneath said first isolation layer.

### Claim 7 (depends on 1)

The device according to claim 1, further comprising:
first connections to external devices; and
second connections to said external devices,
wherein at least a portion of said first connections are underneath said first isolation layer, and
wherein at least a portion of said second connections are above said third isolation layer.

### Claim 8

A 3D semiconductor device, the device comprising:
a first level comprising single crystal first transistors, and a first metal layer, and a second metal layer,
wherein said first level is overlaid by a first isolation layer;
a second level comprising second transistors,
wherein said first isolation layer is overlaid by said second level, and
wherein said second level is overlaid by a second isolation layer;
a third level comprising single crystal third transistors,
wherein said second isolation layer is overlaid by said third level,
wherein said third level is overlaid by a third isolation layer; and
a connective path from said third transistors to said second transistors,
wherein said connective path comprises a via through said second isolation layer,
wherein said third level is bonded to said second isolation layer, and
wherein said bonded comprises at least one oxide to oxide bond.

### Claim 9 (depends on 8)

The device according to claim 8,
wherein said first isolation layer and said second isolation layer are separated by a distance of less than eight microns and greater than 10 nm.

### Claim 10 (depends on 8)

The device according to claim 8,
wherein said second level comprises memory.

### Claim 11 (depends on 8)

The device according to claim 8, further comprising:
a heat removal path from said second transistors to an external surface of said device.

### Claim 12 (depends on 8)

The device according to claim 8, further comprising:
a power delivery path to said second transistors,
wherein at least a portion of said power delivery path is underneath at least one of said second transistors.

### Claim 13 (depends on 8)

The device according to claim 8,
wherein said via has a diameter of less than 400 nm and greater than 5 nm.

### Claim 14 (depends on 8)

The device according to claim 8, further comprising:
first connections to at least one first external device; and
second connections to at least one second external device,
wherein at least a portion of said first connections are underneath said first isolation layer, and
wherein at least a portion of said second connections are above said third isolation layer.

### Claim 15

A 3D semiconductor device, the device comprising:
a first level comprising single crystal first transistors and plurality of interconnecting metal layers,
wherein said first level is overlaid by a first isolation layer;
a second level comprising single crystal second transistors,
wherein said first isolation layer is overlaid by said second level, and
wherein said second level is overlaid by a second isolation layer;
a third level comprising third transistors,
wherein said second isolation layer is overlaid by said third level,
wherein said third level is overlaid by a third isolation layer; and
a connective path from said third transistors to said second transistors,
wherein said connective path comprises a via through said second isolation layer,
wherein said third level is bonded to said second isolation layer, and
wherein said bonded comprises at least one oxide to oxide bond.

### Claim 16 (depends on 15)

The device according to claim 15,
wherein said first isolation layer and said second isolation layer are separated by a distance of less than eight microns and greater than 10 nm.

### Claim 17 (depends on 15)

The device according to claim 15,
wherein said via has a diameter of less than 400 nm and greater than 5 nm.

### Claim 18 (depends on 15)

The device according to claim 15, further comprising:
a heat removal path from said second transistors to an external surface of said device.

### Claim 19 (depends on 15)

The device according to claim 15, further comprising:
a power delivery path to said second transistors,
wherein at least a portion of said power delivery path is underneath at least one of said second transistors.

### Claim 20 (depends on 15)

The device according to claim 15, further comprising:
first connections to at least one first external device; and
second connections to at least one second external device,
wherein at least a portion of said first connections are underneath said first isolation layer, and
wherein at least a portion of said second connections are above said third isolation layer.