# US 2021/0280489 A1 · Chip heat dissipating structure, chip structure, circuit board and supercomputing device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0280489 A1 - Document ID: US20210280489A1 - Status: Published application - Kind: A1 - Application number: 17/327,027 - Filed: 2021-05-21 - Published: 2021-09-09 - Earliest claimed: 2018-11-23 - Assignees: Bitmain Technologies Inc. - Applicants: Bitmain Technologies Inc. - Inventors: Tao ZHOU; Yong GAO - Web page: https://patentgrep.com/patent/US20210280489A1 ## CPC - H10W 40/226: {characterised by projecting parts, e.g. fins to increase surface area (leadframes for cooling H10W70/461)} - H10W 40/778: {in encapsulations} - H10W 40/70: Fillings or auxiliary members in containers or in encapsulations for thermal protection or control - H10W 70/02: of conductive package substrates serving as an interconnection, e.g. of metal plates (manufacture or treatment of leadframes H10W70/04) - H10W 74/014: {using batch processing} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 40/258: {Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/01323: {in liquid form, e.g. by dispensing droplets or by screen printing} - H10W 72/0198: {batch processes} - H10W 72/07352: {changes in structures or sizes} - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/321: {Structures or relative sizes of die-attach connectors} - H10W 72/325: {Die-attach connectors having a filler embedded in a matrix} - H10W 72/352: {comprising metals or metalloids, e.g. solders} - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The present application relates to a chip heat dissipating structure, a chip structure, a circuit board and a supercomputing device, and the chip heat dissipating structure includes a metal layer, where the metal layer is covered on the chip. By adding a metal layer on the top of the chip, the heat sink may be soldered onto the metal layer through a solder layer, so that the heat sink is fixed to the top of the chip; the main component of the solder layer is metal tin, and the metal layer has a higher thermal conductivity than an epoxy resin material mounted on a traditional heat sink, thereby solving a problem of the heat dissipation bottleneck of a resin material in the chip, thus improving a heat dissipation effect of the chip and preventing a large amount of heat from damaging the chip. ## Claims ### Claim 1 A chip heat dissipating structure arranged on a chip, wherein the chip heat dissipating structure comprises a metal layer, the metal layer being covered on the chip. ### Claim 2 (depends on 1) The chip heat dissipating structure according to claim 1, wherein the chip heat dissipating structure further comprises: a heat sink connected with the metal layer. ### Claim 3 (depends on 1) The chip heat dissipating structure according to claim 1, wherein the chip comprises a wafer and a plastic encapsulating structure; and the metal layer is covered on the wafer and the plastic encapsulating structure of the chip. ### Claim 4 (depends on 3) The chip heat dissipating structure according to claim 3, wherein an upper surface of the wafer is exposed. ### Claim 5 (depends on 1) The chip heat dissipating structure according to claim 1, wherein an area of the metal layer is the same as an area of an upper surface of the chip. ### Claim 6 (depends on 1) The chip heat dissipating structure according to claim 1, wherein the metal layer is a silver paste layer. ### Claim 7 (depends on 2) The chip heat dissipating structure according to claim 2, wherein the metal layer is a silver paste layer. ### Claim 8 (depends on 3) The chip heat dissipating structure according to claim 3, wherein the metal layer is a silver paste layer. ### Claim 9 (depends on 4) The chip heat dissipating structure according to claim 4, wherein the metal layer is a silver paste layer. ### Claim 10 (depends on 6) The chip heat dissipating structure according to claim 6, wherein a thickness of the silver paste layer is 1-5 microns. ### Claim 11 (depends on 2) The chip heat dissipating structure according to claim 2, wherein the heat sink is soldered onto the metal layer through a solder layer. ### Claim 12 (depends on 11) The chip heat dissipating structure according to claim 11, wherein a solder in the solder layer is tin. ### Claim 13 (depends on 12) The chip heat dissipating structure according to claim 12, wherein a thickness of the solder layer is 0.1-0.15 millimeters. ### Claim 14 (depends on 11) The chip heat dissipating structure according to claim 11, wherein an area of the solder layer is the same as an area of the metal layer, or an area of the solder layer is the same as an area of a lower surface of the heat sink. ### Claim 15 (depends on 3) The chip heat dissipating structure according to claim 3, wherein, if an upper surface of the wafer is flush with an upper surface of the plastic encapsulating structure, the metal layer is a metal layer with a uniform thickness. ### Claim 16 (depends on 3) The chip heat dissipating structure according to claim 3, wherein, if an upper surface of the wafer is lower than an upper surface of the plastic encapsulating structure, the metal layer is embedded in the plastic encapsulating structure. ### Claim 17 (depends on 3) The chip heat dissipating structure according to claim 3, wherein, if an upper surface of the wafer is higher than an upper surface of the plastic encapsulating structure, the wafer is embedded in the metal layer. ### Claim 18 (depends on 1) A chip structure, comprising a chip body and the chip heat dissipating structure according to claim 1 substantially arranged on the chip body. ### Claim 19 (depends on 18) A circuit board, wherein at least one of the chip structure according to claim 18 is arranged on the circuit board. ### Claim 20 (depends on 19) A supercomputing device, wherein at least one of the circuit board according to claim 19 is arranged in the supercomputing device.