# US 2021/0280488 A9 · Semiconductor device, semiconductor chip and method of manufacturing semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0280488 A9 - Document ID: US20210280488A9 - Status: Published application - Kind: A9 - Application number: 16/760,786 - Filed: 2019-04-25 - Published: 2021-09-09 - Earliest claimed: 2018-04-26 - Assignees: Dynax Semiconductor, Inc. - Applicants: Dynax Semiconductor, Inc. - Inventors: Yi PEI; Gouchun KANG; Linlin SUN - Web page: https://patentgrep.com/patent/US20210280488A9 ## CPC - H10D 64/519: {characterised by their top-view geometrical layouts} - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT} - H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT] - H10D 30/471: {High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]} - H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T} - H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)} - H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates} - H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN} - H10D 64/66: Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Embodiments of the disclosure provide a semiconductor device, a semiconductor chip and a method of manufacturing a semiconductor device, wherein the semiconductor device, includes a substrate, a semiconductor layer formed on the substrate, a plurality of gates, drains, and a plurality of sources formed on a side of the semiconductor layer away from the substrate, the gates located between the sources and the drains, and the gates, sources, and drains located in an active region of the semiconductor device, wherein a gate pitch is formed between any two adjacent gates, the formed respective gate pitches include at least two unequal gate pitches, the maximum gate pitch of the respective gate pitches is within a first preset range determined according to a pitch of two gates at the two outermost ends in the semiconductor device in the gate length direction and a total number of gates of the semiconductor device. ## Claims ### Claim 1 A semiconductor device comprising: a substrate; a semiconductor layer formed on the substrate; and a plurality of gates, a plurality of drains, and a plurality of sources formed on a side of the semiconductor layer away from the substrate, the gates being located between the sources and the drains, and the gates, sources, and drains being located in an active region of the semiconductor device; wherein a gate pitch is formed between any two adjacent gates, wherein the formed respective gate pitches include at least two unequal gate pitches, and wherein the maximum gate pitch of the respective gate pitches is within a first preset range determined according to a pitch of two gates at the two outermost ends in the semiconductor device in the gate length direction and a total number of gates of the semiconductor device. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the first preset range is (L/(n−1), L), and wherein the maximum gate pitch Lmax satisfies the following condition, L n - 1 < L max < L wherein L is the pitch of two gates at the two outermost ends in the semiconductor device in the gate length direction, and wherein n is the total number of gates of the semiconductor device. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the minimum gate pitch of the respective gate pitches is within a second preset range determined according to a pitch of two gates at the two outermost ends in the semiconductor device in the gate length direction and a total number of gates of the semiconductor device, wherein the second preset range is (L/(n−1)2, L/(n−1)), and wherein the minimum gate pitch Lmin satisfies the following condition, L ( n - 1 ) 2 < L min < L n - 1 wherein L is the pitch of two gates at the two outermost ends in the semiconductor device in the gate length direction, and wherein n is the total number of gates of the semiconductor device. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein the maximum gate pitch is located between adjacent gates on both sides of the source, and wherein the minimum gate pitch is located between adjacent gates on both sides of the drain. ### Claim 5 (depends on 3) The semiconductor device according to claim 3, wherein the maximum gate pitch is located at a center position of the active region, while other gate pitches are sequentially arranged in a direction from the center position of the active region to a position away from the center position, and wherein all the other gate pitches are the minimum gate pitches. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein, in a direction from a center position of the active region to a position away from the center position, the respective pitches between adjacent gates on both sides of the source decrease sequentially according to a first fixed value or a first change amount, and wherein the respective pitches between adjacent gates on both sides of the drain decrease sequentially according to a second fixed value or a second change amount. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein a plurality of the gates are interconnected together through a gate pad located in a passive region of the semiconductor device, wherein a plurality of the drains are interconnected together through a drain pad located in the passive region, and wherein a plurality of the sources are respectively connected to a ground electrode located on a side of the substrate away from the semiconductor layer respectively through a plurality of through holes penetrating the substrate and the semiconductor layer. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein the respective gate pitches include at least two gate pitches which are the maximum gate pitch. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein the maximum gate pitch is located at a center position of the active region, and in a direction from the center position of the active region to a position away from the center position, and wherein two pitches of the maximum gate pitch and the minimum gate pitch are arranged alternately. ### Claim 10 (depends on 1) A semiconductor chip, wherein the semiconductor chip comprises a plurality of semiconductor devices according to claim 1, and wherein the plurality of semiconductor devices are connected in parallel. ### Claim 11 (depends on 10) The semiconductor chip according to claim 10, wherein a gate pitch between devices is formed between edge gates of any two adjacent semiconductor devices, and in a direction from the center position of the active region of the semiconductor chip to a position away from the center position, and wherein the gate pitches between devices decrease sequentially according to a third fixed value or a third change amount. ### Claim 12 (depends on 11) The semiconductor chip according to claim 11, wherein the third fixed value or third change amount is less than or equal to twice of the maximum gate pitch inside the semiconductor devices in the semiconductor chip. ### Claim 13 (depends on 10) The semiconductor chip according to claim 10, wherein a plurality of the semiconductor devices includes a center device located at the center of the active region and an edge device away from the center of the active region, and wherein a center gate pitch of the edge device is different from an edge gate pitch of the center device; wherein the center gate pitch of the edge device is a gate pitch formed by two adjacent gates located at the center of the edge device, and wherein the edge gate pitch of the center device is a gate pitch formed by any two adjacent gates away from the center of the center device. ### Claim 14 (depends on 13) The semiconductor chip according to claim 13, wherein the center gate pitch of the center device is different from the center gate pitch of the edge device. ### Claim 15 A semiconductor chip comprising a plurality of semiconductor devices, the plurality of semiconductor devices connected in parallel, each semiconductor device comprising a plurality of gates, a plurality of drains, and a plurality of sources, the gates located between the sources and the drains; wherein, in the semiconductor chip, a gate pitch is formed between any two adjacent gates, wherein the formed respective gate pitches include at least two unequal gate pitches, and wherein the maximum gate pitch of the respective gate pitches is within a first preset range determined according to a pitch of two gates at the two outermost ends in the semiconductor chip in the gate length direction and a total number of gates of the semiconductor chip. ### Claim 16 (depends on 15) The semiconductor chip according to claim 15, wherein in a plurality of the semiconductor devices, all gate pitches in at least one semiconductor device are equal. ### Claim 17 (depends on 15) The semiconductor chip according to claim 15, wherein the edge gate pitches between a plurality of adjacent semiconductor devices are equal or decrease from the center of the active region to both ends. ### Claim 18 (depends on 15) The semiconductor chip according to claim 15, wherein a pitch between gates on both sides of the source inside at least one semiconductor device of the plurality of semiconductor devices is d1, and wherein a pitch between gates on both sides of a drain inside the at least one semiconductor device is d2, where d2≤d1≤2d2. ### Claim 19 A method of manufacturing a semiconductor device, the method comprising: providing a substrate; forming a semiconductor layer on a side of the substrate; and forming a plurality of gates, a plurality of drains, and a plurality of sources on a side of the semiconductor layer away from the substrate, each gate located between one of the sources and one of the drains, and the gates, sources, and drains located in an active region of the semiconductor device; wherein a gate pitch is formed between any two adjacent gates, wherein the formed respective gate pitches include at least two unequal gate pitches, and wherein the maximum gate pitch of the respective gate pitches is within a first preset range determined according to a pitch of two gates at the two outermost ends in the semiconductor device in the gate length direction and a total number of gates of the semiconductor device. ### Claim 20 (depends on 19) The method of manufacturing a semiconductor device according to claim 19, wherein the first preset range is (L/(n−1), L), and wherein the maximum gate pitch Lmax satisfies the following condition, L n - 1 < L max < L wherein the minimum gate pitch of the respective gate pitches is within a second preset range determined according to a pitch of two gates at the two outermost ends in the semiconductor device in the gate length direction and a total number of gates of the semiconductor device, wherein the second preset range is (L/(n−1)2, L/(n−1)), and wherein the minimum gate pitch Lmin satisfies the following condition, L ( n - 1 ) 2 < L min < L n - 1 wherein L is the pitch of two gates at the two outermost ends in the semiconductor device in the gate length direction, and wherein n is the total number of gates of the semiconductor device.