# US 2021/0280487 A1 · Semiconductor die, manufacturing method thereof, and semiconductor package

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- Number: US 2021/0280487 A1
- Document ID: US20210280487A1
- Status: Published application
- Kind: A1
- Application number: 17/327,787
- Filed: 2021-05-24
- Published: 2021-09-09
- Earliest claimed: 2019-08-22
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Jie Chen; Hsien-Wei Chen; Ming-Fa Chen
- Web page: https://patentgrep.com/patent/US20210280487A1

## CPC

- H10W 74/147: {the encapsulations being multilayered}
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/43: Layouts of interconnections
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10W 70/095: {of vias therein}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/687: {characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage}
- H10W 74/01: Manufacture or treatment
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 72/01: {Manufacture or treatment}
- H10W 72/0198: {batch processes}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/921: {Structures or relative sizes of bond pads}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor die includes an interconnection structure, conductive pads, a first passivation layer, and a second passivation layer. The conductive pads are disposed over and electrically connected to the interconnection structure. The first passivation layer and the second passivation layer fill a gap between two adjacent conductive pads. The first passivation layer includes a first section and a second section. The first section extends substantially parallel to a top surface of the interconnection structure. The second section is connected to the first section. The second section is inclined with respect to a side surface of one of the conductive pads. Thicknesses of the first section and the second section are different.

## Claims

### Claim 1

A semiconductor die, comprising:
an interconnection structure;
conductive pads disposed over and electrically connected to the interconnection structure; and
a first passivation layer and a second passivation layer filling a gap between two adjacent conductive pads, and the first passivation layer comprises:
a first section extending substantially parallel to a top surface of the interconnection structure; and
a second section connected to the first section, wherein the second section is inclined with respect to a side surface of one of the conductive pads, and thicknesses of the first section and the second section are different.

### Claim 2 (depends on 1)

The semiconductor die of claim 1, wherein an included angle between the first section and the second section ranges between 100° and 120°.

### Claim 3 (depends on 1)

The semiconductor die of claim 1, further comprising a protective layer disposed between the interconnection structure and the first passivation layer and between portions of the conductive pads and the first passivation layer, wherein the protective layer covers the conductive pads and has openings partially exposing the top surfaces of the conductive pads.

### Claim 4 (depends on 3)

The semiconductor die of claim 3, wherein the first passivation further comprises a third section extending over the conductive pads and the protective layer, and a top surface of the third section of the first passivation layer over the protective layer is located at a level higher than the top surface of the third section of the first passivation layer over the openings.

### Claim 5 (depends on 1)

The semiconductor die of claim 1, wherein the first passivation layer and the second passivation layer are made of a same material.

### Claim 6 (depends on 1)

The semiconductor die of claim 1, wherein the first section is thinner than the second section.

### Claim 7 (depends on 1)

The semiconductor die of claim 1, wherein a ratio of a distance between two adjacent conductive pads and a height of the conductive pads is less than 3.

### Claim 8

A semiconductor package, comprising:
a first semiconductor die, comprising:
a semiconductor substrate;
an interconnection structure disposed on the semiconductor substrate;
conductive pads disposed beside each other on the interconnection structure; and
a composite passivation structure covering the conductive pads, comprising:
a first passivation layer conformally disposed over the conductive pads; and
a second passivation layer disposed on the first passivation layer, wherein the second passivation layer has a first section and second sections located between two adjacent conductive pads, an extending direction of the first section is substantially parallel to a top surface of the interconnection structure, one of the second sections faces a side surface of one of the two adjacent conductive pads, and another one of the second sections faces a side surface of another one of the two adjacent conductive pads, and a thickness of the first section is smaller than a thickness of the second sections; and
a second semiconductor die disposed on and electrically connected to the first semiconductor die.

### Claim 9 (depends on 8)

The semiconductor package of claim 8, wherein at least one of the contact pads has a probe mark protruding from a top surface of the at least one of the contact pads, and the first passivation layer and the second passivation layer respectively have a peak isomorphic with and over the probe mark.

### Claim 10 (depends on 8)

The semiconductor package of claim 8, wherein an included angle between the first section and one of the second sections ranges between 100° and 120°.

### Claim 11 (depends on 8)

The semiconductor package of claim 8, wherein extending directions of the second sections converge toward the first section.

### Claim 12 (depends on 8)

The semiconductor package of claim 8, wherein the composite passivation structure further comprises a third passivation layer covering the second passivation layer.

### Claim 13 (depends on 12)

The semiconductor package of claim 12, wherein the third passivation layer includes a first portion disposed over the first section of the second passivation layer and second portions respectively disposed over the corresponding second sections of the second passivation layer, and the first portion of the third passivation layer has a triangular shape pointing away from the interconnection structure.

### Claim 14 (depends on 8)

The semiconductor package of claim 8, wherein the first semiconductor die has a first bonding layer comprising first bonding pads, the second semiconductor die has a second bonding layer comprising second bonding pads, the first bonding layer is bonded to the second bonding layer, and the first bonding pads are aligned with the corresponding second bonding pads.

### Claim 15

A manufacturing method of a semiconductor die, comprising:
providing a semiconductor wafer having an interconnection structure and conductive pads;
performing a first chemical vapor deposition process to form a first passivation layer conformally covering the conductive pads;
performing a high-density plasma chemical vapor deposition process to form a second passivation layer on the first passivation layer, wherein a thickness of the second passivation layer is non-uniform;
performing a second chemical vapor deposition process to form a third passivation layer on the second passivation layer; and
forming a bonding layer on the third passivation layer.

### Claim 16 (depends on 15)

The manufacturing method of claim 15, wherein during the high-density plasma chemical vapor deposition process, at least a portion of the first passivation layer is removed.

### Claim 17 (depends on 16)

The manufacturing method of claim 16, wherein during the high-density plasma chemical vapor deposition process, edges of the first passivation layer are smoothed.

### Claim 18 (depends on 16)

The manufacturing method of claim 16, wherein during the high-density plasma chemical vapor deposition process, at least a portion of the second passivation layer is removed.

### Claim 19 (depends on 15)

The manufacturing method of claim 15, further comprising forming bonding vias extending through the first passivation layer, the second passivation layer, and the third passivation layer to electrically connect the interconnection structure and the bonding layer.

### Claim 20 (depends on 15)

The manufacturing method of claim 15, further comprising forming a protective layer over the interconnection structure and the conductive pads before forming the first passivation layer.