# US 2021/0280481 A1 · Protection structures in semiconductor chips and methods for forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0280481 A1 - Document ID: US20210280481A1 - Status: Published application - Kind: A1 - Application number: 16/862,320 - Filed: 2020-04-29 - Published: 2021-09-09 - Earliest claimed: 2020-03-03 - Assignees: Yangtze Memory Technologies Co., Ltd. - Applicants: Yangtze Memory Technologies Co., Ltd. - Inventors: Jialan He - Web page: https://patentgrep.com/patent/US20210280481A1 ## CPC - H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) - H10W 74/114: {by a substrate and the encapsulations} - H10W 20/42: Vias, e.g. via plugs - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00) - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 74/124: {the encapsulations having cavities other than that occupied by chips} - H10W 74/134: {the encapsulations being in grooves in the semiconductor body} - H10W 74/47: comprising organic materials, e.g. plastics or resins - H10W 74/129: {forming a chip-scale package [CSP]} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Embodiments of semiconductor chips and fabrication methods thereof are disclosed. In one example, a semiconductor chip includes a main chip region and a protection structure surrounding the main chip region in a plan view. The protection structure includes a dielectric layer and a conductive portion in the dielectric layer. The conductive portion includes a conductive layer and a core having a material different from that of the conductive layer. ## Claims ### Claim 1 A semiconductor chip, comprising: a main chip region; and a protection structure surrounding the main chip region in a plan view and comprising a dielectric layer and a conductive portion in the dielectric layer, wherein the conductive portion comprises a conductive layer and a core having a material different from that of the conductive layer. ### Claim 2 (depends on 1) The semiconductor chip of claim 1, wherein the protection structure comprises a single conductive portion. ### Claim 3 (depends on 1) The semiconductor chip of claim 1, wherein the protection structure comprises four sides connected to enclose the main chip region in the plan view. ### Claim 4 (depends on 1) The semiconductor chip of claim 1, wherein a width of the conductive portion is greater than about 100 nm. ### Claim 5 (depends on 1) The semiconductor chip of claim 1, wherein the conductive portion further comprises a contact above and in contact with the conductive layer in a side view. ### Claim 6 (depends on 5) The semiconductor chip of claim 5, wherein the contact comprises a vertical interconnect access (VIA). ### Claim 7 (depends on 1) The semiconductor chip of claim 1, wherein the material of the core comprises a gap-filling material. ### Claim 8 (depends on 7) The semiconductor chip of claim 7, wherein the gap-filling material comprises at least one of a spin-on coating dielectric (SOD), a spin-on coating carbon (SOC), a fluid organic material, or a fluid inorganic material. ### Claim 9 (depends on 1) The semiconductor chip of claim 1, wherein the conductive layer comprises a metal. ### Claim 10 (depends on 1) The semiconductor chip of claim 1, wherein the core is surrounded by the conductive layer in a side view. ### Claim 11 A semiconductor chip, comprising: a main chip region; and a protection structure surrounding the main chip region in a plan view and comprising a single conductive portion, wherein the single conductive portion comprises a conductive layer and a core surrounded by the conductive layer in a side view. ### Claim 12 A method for forming a protection structure of a semiconductor chip, comprising: forming a trench surrounding a main chip region of the semiconductor chip in a plan view; and forming a conductive portion to fully fill the trench, wherein the conductive portion comprises a conductive layer and a core having a material different from that of the conductive layer. ### Claim 13 (depends on 12) The method of claim 12, further comprising forming a contact above and in contact with the conductive layer. ### Claim 14 (depends on 12) The method of claim 12, wherein a width of the trench is greater than about 100 nm. ### Claim 15 (depends on 12) The method of claim 12, wherein forming the conductive portion comprises: partially filling the trench with a first conductive material; filling a remainder of the trench with a gap-filling material; and planarizing the first conductive material and the gap-filling material until a top of the trench. ### Claim 16 (depends on 15) The method of claim 15, wherein partially filling the trench comprises depositing the first conductive material over a sidewall and a bottom of the trench. ### Claim 17 (depends on 15) The method of claim 15, wherein filling the remainder of the trench comprises spin coating the gap-filling material into the remainder of the trench. ### Claim 18 (depends on 15) The method of claim 15, wherein the gap-filling material comprises at least one of a spin-on coating dielectric (SOD), a spin-on coating carbon (SOC), a fluid organic material, or a fluid inorganic material. ### Claim 19 (depends on 15) The method of claim 15, wherein forming the conductive portion further comprises: etching back a portion of the planarized gap-filling material to form the core and a recess on the core; and filling the recess with a second conductive material to form the conductive layer surrounding the core in a side view. ### Claim 20 (depends on 15) The method of claim 15, wherein forming the conductive portion further comprises: depositing a second conductive material on the planarized conductive material and the planarized gap-filling material; and patterning the second conductive material to form the core and the conductive layer surrounding the core in a side view.