# US 2021/0280476 A1 · Semiconductor substrate, semiconductor package including semiconductor substrate, and test method of semiconductor substrate > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0280476 A1 - Document ID: US20210280476A1 - Status: Published application - Kind: A1 - Application number: 16/997,377 - Filed: 2020-08-19 - Published: 2021-09-09 - Earliest claimed: 2020-03-06 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Bok Gyu MIN - Web page: https://patentgrep.com/patent/US20210280476A1 ## CPC - H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads} - H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers} - H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics} - H10W 70/65: Shapes or dispositions of interconnections - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 72/072: {of bump connectors} - H10W 72/07231: {Techniques} - H10W 72/07236: {Soldering or alloying} - H10W 72/07253: {changes in shapes} - H10W 72/07254: {changes in dispositions} - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/237: {Multiple bump connectors having different shapes} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/248: {Top-view layouts, e.g. mirror arrays} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/944: {Dispositions of multiple bond pads} - H10W 72/951: {Materials of bond pads} - H10W 72/967: {Multiple bond pads having different functions} - H10W 80/743: {having disposition changed during the connecting} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor substrate including an upper surface and a lower surface may include a bump pad unit disposed on the upper surface. The semiconductor substrate may also include test pads disposed on the upper surface or the lower surface. The semiconductor substrate may also include traces configured to connect the bump pad unit and the test pads. The bump pad unit includes a main bump pad disposed on the upper surface, and a plurality of side bump pads disposed on the upper surface to be spaced apart from the main bump pad. The traces may connect the main bump pad and the plurality of side bump pads to the test pads in a one-to-one manner. ## Claims ### Claim 1 A semiconductor substrate comprising an upper surface and a lower surface comprising: a bump pad unit disposed on the upper surface; test pads disposed on the upper surface or the lower surface; and traces configured to connect the bump pad unit and the test pads, wherein the bump pad unit comprises a main bump pad disposed on the upper surface, and a plurality of side bump pads disposed on the upper surface to be spaced apart from the main bump pad, and wherein the traces connect the main bump pad and the plurality of side bump pads to the test pads in a one-to-one manner. ### Claim 2 (depends on 1) The semiconductor substrate of claim 1, wherein the plurality of side bump pads comprise: a first side bump pad disposed on the upper surface of the semiconductor substrate spaced apart from the main bump pad in a first side direction from the main bump pad; and a second side bump pad disposed on the upper surface of the semiconductor substrate spaced apart from the main bump pad in a second side direction from the main bump pad. ### Claim 3 (depends on 2) The semiconductor substrate of claim 2, wherein the first side bump pad and the second side bump pad have the same shape and size, and are disposed to be symmetrical with respect to the main bump pad by being spaced apart from the main bump pad by the same distance in the first and second directions, wherein the first and second directions are opposite directions. ### Claim 4 (depends on 3) The semiconductor substrate of claim 3, wherein: the test pads comprise first, second, and third test pads; the traces comprise first, second, and third traces; the first trace is disposed to electrically connect the main bump pad to the first test pad; the second trace is disposed to electrically connect the first side bump pad to the second test pad; and the third trace is disposed to electrically connect the second side bump pad to the third test pad. ### Claim 5 (depends on 1) The semiconductor substrate of claim 1, wherein: the plurality of side bump pads include first, second, third, and fourth side bump pads; the first side bump pad and the second side bump pad have the same shape and size, are arranged transversely around the main bump pad, and are disposed on the upper surface of the semiconductor substrate to be symmetrical with respect to the main bump pad; and the third side bump pad and the fourth side bump pad have the same shape and size, are arranged longitudinally around the main bump pad, and are disposed on the upper surface of the semiconductor substrate to be symmetrical with respect to the main bump pad. ### Claim 6 (depends on 5) The semiconductor substrate of claim 5, wherein: the test pads comprise first, second, third, fourth, and fifth test pads; the traces comprise first, second, third, fourth, and fifth traces; the first trace is disposed to electrically connect the main bump pad to the first test pad; the second trace is disposed to electrically connect the first side bump pad to the second test pad; the third trace is disposed to electrically connect the second side bump pad to the third test pad; the fourth trace is disposed to electrically connect the third side bump pad to the fourth test pad; and the fifth trace is disposed to electrically connect the fourth side bump pad to the fifth test pad. ### Claim 7 A semiconductor package comprising: a semiconductor substrate including an upper surface and a lower surface; a bump pad unit including a main bump pad disposed on the upper surface, and a plurality of side bump pads disposed on the upper surface to be spaced apart from the main bump pad; bumps bonded to the bump pad unit; test pads disposed on the upper surface or the lower surface; and traces provided in the semiconductor substrate to connect the main bump pad and the plurality of side bump pads to the test pads in a one-to-one manner, wherein the test pads are electrically connected to the main bump pad and the plurality of side bump pads, respectively, such that whether the main bump pad and the plurality of side bump pads are electrically connected is detected by a test signal input from outside of the semiconductor substrate. ### Claim 8 (depends on 7) The semiconductor package of claim 7, further comprising: bonding pads disposed on the upper surface of the semiconductor substrate in a form of a plurality columns; and a semiconductor chip disposed on the bumps to be mounted on the semiconductor substrate. ### Claim 9 (depends on 8) The semiconductor package of claim 8, wherein the bump pad unit is disposed at a center of the semiconductor substrate, and wherein the bumps are disposed on the bump pad unit and the bonding pads to connect the semiconductor chip to the semiconductor substrate. ### Claim 10 (depends on 8) The semiconductor package of claim 8, wherein at least one additional bump pad unit is disposed on the upper surface of the semiconductor substrate, and wherein the additional bumps are disposed on the least one additional bump pad unit and the bonding pads to connect the semiconductor chip to the semiconductor substrate. ### Claim 11 (depends on 8) The semiconductor package of claim 8, wherein the semiconductor package comprises a plurality of bump pad units, wherein the bump pad units are disposed in at least two regions of four corner regions of the semiconductor substrate, and wherein the bumps are disposed on the bump pad units and the bonding pads to connect the semiconductor chip to the semiconductor substrate. ### Claim 12 (depends on 7) The semiconductor package of claim 7, wherein the plurality of side bump pads comprise: a first side bump pad disposed on the upper surface of the semiconductor substrate spaced apart from the main bump pad in a first side direction from the main bump pad; and a second side bump pad disposed on the upper surface of the semiconductor substrate spaced apart from the main bump pad in a second side direction from the main bump pad. ### Claim 13 (depends on 12) The semiconductor package of claim 12, wherein the first side bump pad and the second side bump pad have the same shape and size, and are disposed to be symmetrical with respect to the main bump pad by being spaced apart from the main bump pad by the same distance in the first and second directions, wherein the first and second directions are opposite directions. ### Claim 14 (depends on 13) The semiconductor package of claim 13, wherein: the test pads comprise first, second, and third test pads; the traces comprise first, second, and third traces; the first trace is disposed to electrically connect the main bump pad to the first test pad; the second trace is disposed to electrically connect the first side bump pad to the second test pad; and the third trace is disposed to electrically connect the second side bump pad to the third test pad. ### Claim 15 (depends on 7) The semiconductor package of claim 7, wherein the plurality of side bump pads include first, second, third, and fourth side bump pads, wherein the first side bump pad and the second side bump pad have the same shape and size, are arranged transversely around the main bump pad, and are disposed on the upper surface of the semiconductor substrate to be symmetrical with respect to the main bump pad, and wherein the third side bump pad and the fourth side bump pad have the same shape and size, are arranged longitudinally around the main bump pad, and are disposed on the upper surface of the semiconductor substrate to be symmetrical with respect to the main bump pad. ### Claim 16 (depends on 15) The semiconductor package of claim 15, wherein: the test pads comprise first, second, third, fourth, and fifth test pads; the traces comprise first, second, third, fourth, and fifth traces; the first trace is disposed to electrically connect the main bump pad to the first test pad; the second trace is disposed to electrically connect the first side bump pad to the second test pad; the third trace is disposed to electrically connect the second side bump pad to the third test pad; the fourth trace is disposed to electrically connect the third side bump pad to the fourth test pad; and the fifth trace is disposed to electrically connect the fourth side bump pad to the fifth test pad.