# US 2021/0280472 A1 · Semiconductor structure and method for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0280472 A1 - Document ID: US20210280472A1 - Status: Published application - Kind: A1 - Application number: 17/330,256 - Filed: 2021-05-25 - Published: 2021-09-09 - Earliest claimed: 2018-07-31 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company Ltd. - Inventors: SUNG-LI WANG; PENG-WEI CHU; YASUTOSHI OKUNO - Web page: https://patentgrep.com/patent/US20210280472A1 ## CPC - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 30/0212: {using self-aligned silicidation} - H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability} - H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates} - H10D 30/6219: {characterised by the source or drain electrodes} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 64/0112: {using conductive layers comprising silicides} - H10D 84/0193: {the components including FinFETs} - H10D 84/853: {comprising FinFETs} - H10P 14/6349: {Deposition of epitaxial materials} - H10P 95/90: Thermal treatments, e.g. annealing or sintering - H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers} - H10P 50/00: Etching of wafers, substrates or parts of devices - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor structure includes a substrate, a first silicide, and a second silicide. The substrate has a first epitaxy region in a first transistor of a first conductive type and a second epitaxy region in a second transistor of a second conductive type. The first silicide is on the first epitaxy region, the first silicide comprising a first metal and a second metal, and the second silicide is on the second epitaxy region. A work function of the first silicide is greater than a work function of the second silicide. ## Claims ### Claim 1 A semiconductor structure, comprising: a substrate having a first epitaxy region in a first transistor of a first conductive type and a second epitaxy region in a second transistor of a second conductive type; a first silicide on the first epitaxy region, the first silicide comprising a first metal and a second metal; and a second silicide on the second epitaxy region, wherein a work function of the first silicide is greater than a work function of the second silicide. ### Claim 2 (depends on 1) The semiconductor structure of claim 1, wherein the second silicide comprises one of the first metal and the second metal. ### Claim 3 (depends on 2) The semiconductor structure of claim 2, wherein the second silicide comprises the second metal, and a work function of the first metal layer is greater than a work function of the second metal layer. ### Claim 4 (depends on 3) The semiconductor structure of claim 3, wherein the first metal comprises at least one of ruthenium (Ru), cobalt (Co), nickel (Ni), platinum (Pt), and tungsten (W). ### Claim 5 (depends on 3) The semiconductor structure of claim 3, and the second metal comprises at least on of titanium (Ti), tantalum (Ta), erbium (Er), yttrium (Y), ytterbium (Yb), europium (Eu), terbium (Tb), lutetium (Lu), thorium (Th), scandium (Sc), hafnium (Hf), zirconium (Zr), and terbium (Tb). ### Claim 6 (depends on 1) The semiconductor structure of claim 1, wherein the first epitaxy region is in a PFET, and the second epitaxy region is in an NFET. ### Claim 7 (depends on 1) The semiconductor structure of claim 1, wherein the first epitaxy region comprises a germanium-rich surface. ### Claim 8 (depends on 1) The semiconductor structure of claim 1, further comprising a germanium (Ge) cap layer over the first epitaxy region. ### Claim 9 A semiconductor structure, comprising: a substrate having a first epitaxy region in a first transistor and a second epitaxy region in a second transistor, the first epitaxy region having a first germanium concentration greater than 50%; a first silicide on the first epitaxy region, the first silicide comprising a first metal and a second metal; and a second silicide on the second epitaxy region, wherein a work function of the first silicide is greater than a work function of the second silicide. ### Claim 10 (depends on 9) The semiconductor structure of claim 9, wherein the second silicide comprises one of the first metal and the second metal. ### Claim 11 (depends on 10) The semiconductor structure of claim 10, wherein the second silicide comprises the second metal, and a work function of the first metal layer is greater than a work function of the second metal layer. ### Claim 12 (depends on 11) The semiconductor structure of claim 11, wherein the first metal comprises at least one of ruthenium (Ru), cobalt (Co), nickel (Ni), platinum (Pt), and tungsten (W). ### Claim 13 (depends on 12) The semiconductor structure of claim 12, and the second metal comprises at least on of titanium (Ti), tantalum (Ta), erbium (Er), yttrium (Y), ytterbium (Yb), europium (Eu), terbium (Tb), lutetium (Lu), thorium (Th), scandium (Sc), hafnium (Hf), zirconium (Zr), and terbium (Tb). ### Claim 14 (depends on 9) The semiconductor structure of claim 9, wherein the first transistor is of a first conductive type, and the second transistor is of a second conductive type. ### Claim 15 A method for manufacturing a semiconductor structure, comprising: receiving a substrate having a first epitaxy region in a first transistor of a first conductive type and a second epitaxy region in a second transistor of a second conductive type, wherein the first epitaxy region has a first germanium concentration greater than 50%; introducing an agent directly onto the first epitaxy region and the second epitaxy region, wherein the agent is selectively deposited on the second epitaxy region; selectively depositing a first metal layer on the first epitaxy region; and depositing a second metal layer on the first epitaxy region and the second epitaxy region. ### Claim 16 (depends on 15) The method of claim 15, wherein the agent is a silylation agent bonding with hydroxyl groups on a surface of the second epitaxy region. ### Claim 17 (depends on 15) The method of claim 15, wherein the first epitaxy region is in a PFET, and the second epitaxy region is in an NFET. ### Claim 18 (depends on 15) The method of claim 15, wherein the first epitaxy region comprises a germanium-rich surface. ### Claim 19 (depends on 15) The method of claim 15, further comprising removing the agent from the second epitaxy region prior to depositing the second metal layer. ### Claim 20 (depends on 15) The method of claim 15, further comprising annealing the first metal layer and the second metal layer after depositing the second metal layer.