# US 2021/0280455 A1 · Method of manufacturing semiconductor devices

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- Number: US 2021/0280455 A1
- Document ID: US20210280455A1
- Status: Published application
- Kind: A1
- Application number: 17/316,555
- Filed: 2021-05-10
- Published: 2021-09-09
- Earliest claimed: 2018-06-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ru-Gun LIU; Chin-Hsiang LIN; Chih-Ming LAI; Wei-Liang LIN; Yung-Sung YEN
- Web page: https://patentgrep.com/patent/US20210280455A1

## CPC

- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10P 50/242: {of Group IV materials}
- H10P 50/267: {using plasmas}
- H10P 50/283: {by chemical means}
- H10P 50/696: {Process specially adapted to improve the resolution of the mask}
- H10P 50/73: {using masks for insulating materials}
- H10P 72/7618: {characterised by a movable susceptor, stage or support, others than those only rotating on their own vertical axis, e.g. susceptors on a rotating carrousel}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/085: {involving intermediate temporary filling with material}
- H01J 37/32357: {Generation remote from the workpiece, e.g. down-stream}
- H10W 20/0765: {the thin functional dielectric layers being temporary, e.g. sacrificial layers}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H)

## Abstract

In accordance with an aspect of the present disclosure, in a pattern forming method for a semiconductor device, a first opening is formed in an underlying layer disposed over a substrate. The first opening is expanded in a first axis by directional etching to form a first groove in the underlying layer. A resist pattern is formed over the underlying layer. The resist pattern includes a second opening only partially overlapping the first groove. The underlying layer is patterned by using the resist pattern as an etching mask to form a second groove.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
forming a first underlying layer over a substrate;
forming a second underlying layer over the first underlying layer;
forming a first resist pattern having a first opening over the second underlying layer;
patterning the first and second underlying layers by using the first resist pattern as an etching mask, thereby forming a second opening in the first and second underlying layers;
expanding the second opening in a first axis by directional etching of the second underlying layer to form a first groove in the second underlying layer so that a part of an upper surface of the first underlying layer is exposed around the second opening in the first underlying layer;
forming a second resist pattern including a fourth opening partially overlapping the first groove; and
patterning the second underlying layer by using the second resist pattern as an etching mask to form a first trench in the second underlying layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein in the directional etching, an etching rate of the second underlying layer along the first axis is greater than an etching rate of the second underlying layer along a second axis perpendicular to the first axis.

### Claim 3 (depends on 2)

The method of claim 2, wherein the etching rate of the second underlying layer along the first axis is twice or more the etching rate of the second underlying layer along the second axis perpendicular to the first axis.

### Claim 4 (depends on 1)

The method of claim 1, wherein a width of the first trench is greater than a width of the first groove in the first axis.

### Claim 5 (depends on 4)

The method of claim 4, wherein a width of the second opening at the upper surface of the first underlying layer is smaller than the width of the first trench.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first underlying layer includes a first layer and a second layer formed over the first layer and made of a different material than the first layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein the first layer includes one or more of silicon oxide, silicon nitride, SiON, SiCN, SiOC or SiOCN.

### Claim 8 (depends on 6)

The method of claim 6, wherein the second layer includes one or more of AN, aluminum oxide, AlON, hafnium oxide or zirconium oxide.

### Claim 9 (depends on 6)

The method of claim 6, wherein the second underlying layer includes one or more of silicon oxide, silicon nitride, SiON, SiCN, SiOC or SiOCN.

### Claim 10 (depends on 6)

The method of claim 6, wherein the second underlying layer includes one or more of TiN, or TaN.

### Claim 11 (depends on 1)

The method of claim 1, wherein the second resist pattern fills the second opening formed in the first underlying layer.

### Claim 12

A method for manufacturing a semiconductor device, the method comprising:
forming a first opening in an underlying layer disposed over a substrate;
forming a sacrificial layer on an inner wall of the first opening by a directional deposition method;
expanding an upper part of the first opening in a first axis by a directional etching method to form a first groove in the underlying layer;
forming a resist pattern over the underlying layer, the resist pattern including a second opening only partially overlapping the first groove; and
patterning the underlying layer by using the resist pattern as an etching mask to form a second groove.

### Claim 13 (depends on 12)

The method of claim 12, wherein a deposition amount of the sacrificial layer in the first axis is greater than a deposition amount of the sacrificial layer in a second axis perpendicular to the first axis.

### Claim 14 (depends on 13)

The method of claim 13, wherein the deposition amount of the sacrificial layer in the first axis is twice or more the deposition amount of the sacrificial layer in the second axis.

### Claim 15 (depends on 13)

The method of claim 13, further comprising, after expanding the upper part of the first opening, removing the sacrificial layer.

### Claim 16 (depends on 13)

The method of claim 13, wherein the sacrificial layer includes one or more of silicon oxide, silicon nitride, SiON, SiOCN, SiON, SiCN or an organic material.

### Claim 17

A method for manufacturing a semiconductor device, the method comprising:
forming a underlying conductive pattern in an dielectric layer over a substrate;
forming a underlying layer over the underlying conductive pattern and the dielectric layer;
forming a first opening in an underlying layer;
expanding an upper portion of the first opening in a first axis by directional etching to form a first groove in an upper portion of the underlying layer;
forming a resist pattern over the underlying layer, the resist pattern including a second opening partially overlapping the first groove;
patterning the upper portion of the underlying layer by using the resist pattern as an etching mask to form a second groove; and
filling a conductive material in the second groove and the lower portion of the first opening in an lower portion of the underlying layer to connect the underlying conductive pattern.

### Claim 18 (depends on 17)

The method of claim 17, wherein the forming the resist pattern comprises:
forming a first resist layer over the underlying layer to fill the lower portion of the first opening and the expanded upper portion of the first opening;
forming a second resist layer having an opening corresponding to the second opening over the first resist layer;
patterning the first resist layer by using the second resist layer as an etching mask; and
removing the second resist layer.

### Claim 19 (depends on 17)

The method of claim 17, further comprising, before expanding the upper portion of the first opening, forming a sacrificial layer on an inner wall of the first opening by a directional deposition method.

### Claim 20 (depends on 17)

The method of claim 17, wherein, when viewed from above, a width of the conductive material above the first opening is smaller than a width of the conductive material above a location other than the first opening.