# US 2021/0280430 A1 · Semiconductor memory structure and method for forming the same

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- Number: US 2021/0280430 A1
- Document ID: US20210280430A1
- Status: Published application
- Kind: A1
- Application number: 16/810,135
- Filed: 2020-03-05
- Published: 2021-09-09
- Earliest claimed: 2020-03-05
- Assignees: Winbond Electronics Corp.
- Applicants: Winbond Electronics Corp.
- Inventors: Shuen-Hsiang KE; Shih-Chieh LIN
- Web page: https://patentgrep.com/patent/US20210280430A1

## CPC

- H10B 12/488: {Word lines}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/482: {Bit lines}
- H10P 14/6548: {by forming intermediate materials, e.g. capping layers or diffusion barriers}
- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 72/50: Bond wires
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming a semiconductor memory structure includes forming a hard mask layer over a semiconductor substrate, etching the hard mask layer to form first mask patterns and second mask patterns, transferring the first and second mask patterns to the substrate to form semiconductor blocks, and thinning down the second mask element. After thinning down the second mask element, the thickness of the second mask elements is less than the thickness of the first mask elements. The method also includes forming a first capping layer to laterally extend over the first mask patterns and the second mask patterns, and etching the first capping layer and the second mask pattern to form contact openings.

## Claims

### Claim 1

A method for forming a semiconductor memory structure, comprising:
forming a hard mask layer over a semiconductor substrate;
etching the hard mask layer to form a plurality of first mask patterns and a plurality of second mask patterns;
transferring the plurality of first mask patterns and the plurality of second mask patterns to the semiconductor substrate to form a plurality of semiconductor blocks;
thinning down the plurality of second mask patterns, wherein a thickness of the plurality of second mask patterns is less than a thickness of the plurality of first mask patterns after thinning down the plurality of second mask patterns;
forming a first capping layer that extends laterally over the plurality of first mask patterns and the plurality of second mask patterns; and
etching the first capping layer and the plurality of second mask patterns to form a plurality of contact openings.

### Claim 2 (depends on 1)

The method for forming the semiconductor memory structure as claimed in claim 1, further comprising:
forming a patterned layer over the hard mask layer, wherein the pattered layer comprises a plurality of third mask patterns and a plurality of fourth mask patterns, wherein the hard mask layer is etched using the patterned layer and the plurality of third mask patterns corresponds to the plurality of first mask patterns and the plurality of fourth mask patterns corresponds to the second mask patterns.

### Claim 3 (depends on 2)

The method for forming the semiconductor memory structure as claimed in claim 2, wherein:
a thickness of the plurality of third mask patterns is greater than a thickness of the plurality of fourth mask patterns, and
the plurality of third mask patterns is made of a different material than the plurality of fourth mask patterns.

### Claim 4 (depends on 2)

The method for forming the semiconductor memory structure as claimed in claim 2, wherein forming the patterned layer further comprises:
forming a semiconductor layer over the hard mask layer;
patterning the semiconductor layer to form the plurality of third mask patterns;
forming a conformal layer along the plurality of third mask patterns and the hard mask layer;
forming a fill layer over the conformal layer between the plurality of third mask patterns;
removing portions of the conformal layer uncovered by the fill layer; and
removing the fill layer, thereby leaving the conformal layer to act as the plurality of fourth mask patterns.

### Claim 5 (depends on 2)

The method for forming the semiconductor memory structure as claimed in claim 2, wherein the hard mask layer comprises a first hard mask layer formed over the semiconductor substrate and a second hard mask layer formed over the first hard mask layer, wherein etching the hard mask layer comprises:
transferring the plurality of third mask patterns and the plurality of fourth mask patterns to the second hard mask layer to form a plurality of fifth mask patterns and a plurality of sixth mask patterns; and
transferring the plurality of fifth mask patterns and the plurality of sixth mask patterns to the first hard mask layer to form the plurality of first mask patterns and the plurality of second mask patterns,
wherein a thickness of the plurality of fifth mask patterns is greater than a thickness of the plurality of sixth mask patterns after forming the plurality of first mask patterns and the plurality of second mask patterns.

### Claim 6 (depends on 5)

The method for forming the semiconductor memory structure as claimed in claim 5, wherein thinning down the plurality of second mask patterns comprises:
removing the plurality of sixth mask patterns; and
recessing the plurality of second mask patterns while the plurality of first mask patterns is covered by the plurality of fifth mask patterns.

### Claim 7 (depends on 1)

The method for forming the semiconductor memory structure as claimed in claim 1, further comprising:
forming a word line in a lower portion of a trench between the plurality of semiconductor blocks, wherein the first capping layer is formed to fill an upper portion of the trench.

### Claim 8 (depends on 1)

The method for forming the semiconductor memory structure as claimed in claim 1, wherein the first capping layer comprises a horizontally extending portion over the plurality of first mask patterns and the plurality of second mask patterns, and the horizontally extending portion has an alternating-convex-concave profile.

### Claim 9 (depends on 8)

The method for forming the semiconductor structure as claimed in claim 8, wherein the horizontally extending portion has convex portions corresponding to the first mask patterns and concave portions corresponding to the second mask patterns.

### Claim 10 (depends on 8)

The method for forming the semiconductor memory structure as claimed in claim 8, further comprising:
forming a second capping layer that extends laterally over the first capping layer, wherein the second capping layer conforms to the first capping layer to have an alternating-convex-concave profile, the second capping layer has second convex portions corresponding to the first mask patterns, and adjacent two of the second convex portions are close to one another to form a void having an upwardly tapered profile, and wherein etching the first capping layer comprises etching the second capping layer to form the contact openings; and
forming contact plugs in the contact openings.

### Claim 11 (depends on 10)

The method for forming the semiconductor memory structure as claimed in claim 10, wherein the voids between the second convex portions of the second capping layer are enlarged to form the contact openings.

### Claim 12 (depends on 10)

The method for forming the semiconductor memory structure as claimed in claim 10, further comprising:
removing portions of the first capping layer above the plurality of first mask patterns to expose the plurality of first mask patterns; and
forming a bit line over the plurality of first mask patterns and the contact plugs.

### Claim 13

A semiconductor memory structure, comprising:
an active region of a semiconductor substrate, comprising a first semiconductor block;
a word line disposed adjacent to the first semiconductor block in the semiconductor substrate;
a mask pattern disposed over the first semiconductor block; and
a capping layer disposed alongside the mask pattern and in the semiconductor substrate to abut the word line, wherein an upper surface of the capping layer is substantially coplanar with an upper surface of the mask pattern.

### Claim 14 (depends on 13)

The semiconductor memory structure as claimed in claim 13, wherein the active region comprises a second semiconductor block, and the semiconductor memory structure further comprises:
a contact plug embedded in the capping layer and disposed over the second semiconductor block.

### Claim 15 (depends on 14)

The semiconductor memory structure as claimed in claim 14, wherein the upper surface of the mask pattern is substantially coplanar with an upper surface of the contact plug.

### Claim 16 (depends on 14)

The semiconductor memory structure as claimed in claim 14, further comprising:
a bit line disposed over the mask pattern, the capping layer and the contact plug.

### Claim 17 (depends on 13)

The semiconductor memory structure as claimed in claim 13, further comprising:
an isolation feature disposed in the semiconductor substrate, wherein a portion of the word line is disposed in the isolation feature, and the mask pattern covers a portion of the isolation feature.

### Claim 18 (depends on 13)

The semiconductor memory structure as claimed in claim 13, wherein the capping layer is made of silicon nitride or silicon oxide.

### Claim 19 (depends on 13)

The semiconductor memory structure as claimed in claim 13, further comprising;
a second active region adjacent to the first active region, wherein the second active region comprises a third semiconductor block covered by the mask pattern.

### Claim 20 (depends on 13)

The semiconductor memory structure as claimed in claim 13, wherein the mask pattern is made of silicon oxide.