# US 2021/0280427 A1 · Contact structures with deposited silicide layers

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- Number: US 2021/0280427 A1
- Document ID: US20210280427A1
- Status: Published application
- Kind: A1
- Application number: 17/329,024
- Filed: 2021-05-24
- Published: 2021-09-09
- Earliest claimed: 2018-09-21
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Sung-Li WANG; Yasutoshi OKUNO; Shih-Chuan CHIU
- Web page: https://patentgrep.com/patent/US20210280427A1

## CPC

- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/01125: {the silicides being formed by chemical reaction with the semiconductor after the contact hole formation}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10P 14/432: {using selective deposition}
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/83125: {the IGFETs characterised by having shared source or drain regions}
- H10W 20/047: {by introducing additional elements therein}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a semiconductor device includes forming a source/drain region on a substrate, depositing a metal-rich metal silicide layer on the source/drain region, depositing a silicon-rich metal silicide layer on the metal-rich metal silicide layer, and forming a contact plug on the silicon-rich metal silicide layer. This disclosure also describes a semiconductor device including a fin structure on a substrate, a source/drain region on the fin structure, a metal-rich metal silicide layer on the source/drain region, a silicon-rich metal silicide layer on the metal-rich metal silicide layer, and a contact plug on the silicon-rich metal silicide layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a fin structure disposed on a substrate;
a source/drain region (S/D) disposed on the fin structure;
a metal-rich silicide layer disposed within the source/drain (S/D) region;
a silicon-rich silicide layer disposed on the metal-rich silicide layer; and
a contact plug disposed on the silicon-rich silicide layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the silicon-rich silicide layer vertically extends over a top surface of the S/D region.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the metal-rich silicide layer comprises an atomic concentration ratio of metal to silicon between about 3:1 and about 1:1.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the silicon-rich silicide layer comprises an atomic concentration ratio of metal to silicon between about 1:1 and about 1:2.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein a thickness of the silicon-rich silicide layer is greater than a thickness of the metal-rich metal silicide layer.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein a thickness of the metal-rich silicide layer is between about 1 nm and about 3 nm.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein a thickness of the silicon-rich silicide layer is between about 4 nm and about 10 nm.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising a silicide liner disposed along sidewalls of the contact plug.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, further comprising a silicide liner disposed on the silicon-rich silicide layer.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein a ratio of a thickness of the silicide liner to a thickness of the silicon-rich silicide layer is between about 1:2 and about 1:10.

### Claim 11

A semiconductor device, comprising:
a fin structure disposed on a substrate;
a merged source/drain region (S/D) disposed on the fin structure;
a metal-rich silicide layer disposed within the merged S/D region;
a silicon-rich metal silicide layer disposed on the metal-rich silicide layer; and
a contact plug disposed on the silicon-rich silicide layer.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein a concentration of metal atoms is greater than a concentration of silicon atoms in the metal-rich silicide layer.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, wherein a concentration of silicon atoms is greater than a concentration of metal atoms in the silicon-rich metal silicide layer.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, wherein the metal-rich silicide layer comprises an atomic concentration ratio of metal to silicon between about 3:1 and about 1:1.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, wherein the silicon-rich metal silicide layer comprises an atomic concentration ratio of metal to silicon between about 1:1 and about 1:2.

### Claim 16

A semiconductor device, comprising:
a fin structure disposed on a substrate;
a source/drain region (S/D) disposed on the fin structure;
a gate structure disposed on the fin structure;
a metal-rich silicide layer disposed within the merged S/D region;
a contact plug disposed over the metal-rich silicide layer; and
a silicide liner disposed along sidewalls of the contact plug.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein a silicon-rich silicide layer is disposed between the metal-rich silicide layer and the contact plug.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein a horizontal dimension of the metal-rich silicide layer is greater than a horizontal dimension of the silicon-rich silicide layer.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein a ratio of a width of the metal-rich silicide layer to a width of the silicon-rich silicide layer is between about 1:1 and about 5:1.

### Claim 20 (depends on 17)

The semiconductor device of claim 17, wherein a ratio of a thickness of the silicide liner to a thickness of the silicon-rich silicide layer is between about 1:2 and about 1:10.