# US 2021/0280425 A1 · Semiconductor device structure with fine patterns and method for forming the same

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- Number: US 2021/0280425 A1
- Document ID: US20210280425A1
- Status: Published application
- Kind: A1
- Application number: 16/810,328
- Filed: 2020-03-05
- Published: 2021-09-09
- Earliest claimed: 2020-03-05
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Yi-Hsien CHOU
- Web page: https://patentgrep.com/patent/US20210280425A1

## CPC

- H10D 64/01334: {by defining the insulator using a sidewall spacer mask, a transformation under a mask or a plating at a sidewall}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/2041: {Photolithographic processes}
- H10P 76/4083: {characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a semiconductor device structure with fine patterns and a method for forming the semiconductor device structure, which can prevent the collapse of the fine patterns. The semiconductor device structure includes a first target structure and a second target structure disposed over a semiconductor substrate. The semiconductor device structure also includes a first spacer element disposed over the first target structure, wherein a topmost point of the first spacer element is between a central line of the first target structure and a central line of the second target structure in a cross-sectional view.

## Claims

### Claim 1

A semiconductor device structure, comprising:
a first target structure and a second target structure disposed over a semiconductor substrate; and
a first spacer element disposed over the first target structure, wherein a topmost point of the first spacer element is between a central line of the first target structure and a central line of the second target structure in a cross-sectional view;
wherein the first spacer element has a rounding top surface in the cross-sectional view, and the topmost point of the first spacer element is disposed between two ends of the rounding top surface of the first spacer element.

### Claim 2 (depends on 1)

The semiconductor device structure of claim 1, further comprising:
a second spacer element disposed over the second target structure, wherein a topmost point of the second spacer element is between the central line of the first target structure and the central line of the second target structure in the cross-sectional view.

### Claim 3 (depends on 1)

The semiconductor device structure of claim 1, wherein the first target structure has a high etching selectivity against the first spacer element.

### Claim 4 (depends on 1)

The semiconductor device structure of claim 1, wherein the first target structure and the second target structure are made of a thermal decomposable material, a photonic decomposable material, or an e-beam decomposable material.

### Claim 5 (depends on 1)

The semiconductor device structure of claim 1, wherein a top surface of the semiconductor substrate is exposed between the first target structure and the second target structure.

### Claim 6

(canceled)

### Claim 7 (depends on 26)

The semiconductor device structure of claim 26, wherein the second spacer element has a rounding top surface in the cross-sectional view, and the topmost point of the second spacer element is disposed between two ends of the rounding top surface of the second spacer element.

### Claim 8 (depends on 1)

The semiconductor device structure of claim 1, wherein the first spacer element and the second spacer element are substantially symmetric with respect to a middle line between the first spacer element and the second spacer element.

### Claim 9 (depends on 1)

The semiconductor device structure of claim 1, wherein the first target structure has a first top width, the first spacer element has a first bottom width, and the first top width is substantially the same as the first bottom width.

### Claim 10 (depends on 2)

The semiconductor device structure of claim 2, wherein the second target structure has a second top width, the second spacer element has a second bottom width, and the second top width is substantially the same as the second bottom width.

### Claim 11 (depends on 1)

The semiconductor device structure of claim 1, wherein the first spacer element has an inner surface and an outer surface, the inner surface faces the central line in the cross-sectional view, the inner surface is substantially a non-curved surface, and the outer surface is substantially a curved surface.

### Claim 12 (depends on 11)

The semiconductor device structure of claim 11, wherein the first spacer element has an inner surface and an outer surface, the inner surface faces the central line in the cross-sectional view, and the curvature of the inner surface is smaller than that of the outer surface.

### Claim 13

A method for preparing a semiconductor device structure, comprising:
forming a target material over a semiconductor substrate;
forming a plurality of energy removable patterns over the target material;
forming a plurality of spacers respectively on sidewall surfaces of the energy removable patterns;
forming a dielectric layer surrounding the plurality of energy removable patterns and the plurality of spacers; and
etching the plurality of energy removable patterns, the dielectric layer and the target material by using the plurality of spacers as an etching mask to form a plurality of target structures;
wherein each of the plurality of spacers includes a rounding top surface in the cross-sectional view, and a topmost point of each of the plurality of spacers is disposed between two ends of the rounding top surface of each of the plurality of spacers;
wherein the topmost point of the each of the plurality of spacers is between central lines of adjacent two of the plurality of target structures in a cross-sectional view.

### Claim 14 (depends on 13)

The method of claim 13, wherein forming a plurality of spacers respectively on sidewall surfaces of the energy removable patterns comprises:
conformally forming a spacer material over top surfaces and sidewall surfaces of the plurality of energy removable patterns and over a top surface of the target material; and
performing an anisotropic etching process to remove a portion of the spacer material such that the plurality of spacers are formed over the sidewall surfaces of the plurality of energy removable patterns.

### Claim 15 (depends on 14)

The method of claim 14, wherein the energy removable patterns has a first etching selectivity against the plurality spacers, the dielectric layer has a second etching selectivity against the plurality spacers and the first etching selectivity and the second etching selectivity are similar to each other.

### Claim 16 (depends on 14)

The method of claim 14, wherein the energy removable patterns has a first etching selectivity against the plurality spacers, the target material has a third etching selectivity against the plurality of spacers, and the first etching selectivity and the third etching selectivity are similar to each other.

### Claim 17 (depends on 14)

The method of claim 14, wherein the dielectric layer has a second etching selectivity against the plurality spacers, the target material has a third etching selectivity against the plurality of spacers, and the second etching selectivity and the third etching selectivity are similar to each other.

### Claim 18 (depends on 13)

The method of claim 13, wherein the dielectric layer and the plurality of energy removable patterns include a thermal decomposable material.

### Claim 19 (depends on 13)

The method of claim 13, wherein the dielectric layer and the plurality of energy removable patterns include a photonic decomposable material or an e-beam decomposable material.

### Claim 20 (depends on 13)

The method of claim 13, wherein the dielectric layer and the plurality of energy removable patterns include a base material and a decomposable porogen material that is substantially removed upon exposure to an energy source, the base material includes hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ), porous polyarylether (PAE), porous SiLK, or porous silicon oxide (SiO2), and the decomposable porogen material includes a porogen organic compound.