# US 2021/0280415 A1 · Semiconductor Devices and Methods of Manufacture

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- Number: US 2021/0280415 A1
- Document ID: US20210280415A1
- Status: Published application
- Kind: A1
- Application number: 17/321,691
- Filed: 2021-05-17
- Published: 2021-09-09
- Earliest claimed: 2019-08-23
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chun-Yen Peng; Te-Yang Lai; Sai-Hooi Yeong; Chi On Chui
- Web page: https://patentgrep.com/patent/US20210280415A1

## CPC

- H10P 14/3466: {Crystal orientation}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/0134: {with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor}
- H10D 64/514: {characterised by the insulating layers}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10P 14/3802: {Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth}
- H10P 14/6532: {by exposure to a plasma}
- H10P 14/6544: {to change the morphology of the insulating materials, e.g. transformation of an amorphous layer into a crystalline layer}
- H10P 14/69392: {the material containing hafnium, e.g. HfO2}
- H10P 30/40: into insulating materials
- H10W 20/042: {the barrier, adhesion or liner layers being seed or nucleation layers}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming a crystalline high-k dielectric layer and controlling the crystalline phase and orientation of the crystal growth of the high-k dielectric layer during an anneal process. The crystalline phase and orientation of the crystal growth of the dielectric layer may be controlled using seeding sections of the dielectric layer serving as nucleation sites and using a capping layer mask during the anneal process. The location of the nucleation sites and the arrangement of the capping layer allow the orientation and phase of the crystal growth of the dielectric layer to be controlled during the anneal process. Based on the dopants and the process controls used the phase can be modified to increase the permittivity and/or the ferroelectric property of the dielectric layer.

## Claims

### Claim 1

A semiconductor device comprising:
a channel region within a semiconductor material;
a crystallized dielectric layer adjacent to the channel region, the crystallized dielectric layer having a thickness no greater than 2 nm; and
a gate electrode adjacent to the crystallized dielectric layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the crystallized dielectric layer is fully crystallized.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the crystallized dielectric layer is partially crystallized.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the channel region is part of a semiconductor fin.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the channel region is part of a planar transistor.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the crystallized dielectric layer comprises hafnium oxide.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the crystallized dielectric layer has a concentration gradient of an inert element.

### Claim 8

A semiconductor device comprising:
a gate dielectric overlying a channel region of a semiconductor fin, the gate dielectric comprising a crystallized region that is less than 3 nm thick;
a dopant embedded within the crystallized region, the dopant having a concentration gradient within the crystallized region; and
a gate electrode located on an opposite side of the gate dielectric from the channel region.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the gate dielectric comprises hafnium oxide.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the dopant is zirconium.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein the dopant comprises an inert element.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein the crystallized region fills the entire gate dielectric.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, wherein the gate dielectric further comprises an amorphous region.

### Claim 14 (depends on 8)

The semiconductor device of claim 8, wherein the crystallized region has a grain size of between about 30 Å and about 100 Å.

### Claim 15

A semiconductor device, comprising:
a semiconductor fin over a semiconductor substrate;
a gate dielectric over the semiconductor fin, the gate dielectric having a thickness of less than 3 nm and having a first crystalline orientation;
a capping layer adjacent to and in physical contact with at least a portion of the gate dielectric; and
a gate electrode overlying the gate dielectric and the capping layer, the gate electrode extending through the capping layer to physically contact a portion of the gate dielectric.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the gate dielectric is hafnium oxide.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, further comprising a capping layer located between the gate dielectric and the gate electrode, wherein the gate electrode is in physical contact with a portion of the gate dielectric.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein the first crystalline orientation is a tetragonal orientation.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, wherein the first crystalline orientation is a cubic orientation.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, wherein the gate dielectric comprises a concentration gradient of an inert element, wherein a concentration of the inert element increases as the gate dielectric extends away from the semiconductor substrate.