# US 2021/0280412 A1 · Semiconductor component and method for fabricating the same

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- Number: US 2021/0280412 A1
- Document ID: US20210280412A1
- Status: Published application
- Kind: A1
- Application number: 16/812,589
- Filed: 2020-03-09
- Published: 2021-09-09
- Earliest claimed: 2020-03-09
- Assignees: Xia Tai Xin Semiconductor (Qing Dao) Ltd.
- Applicants: Xia Tai Xin Semiconductor (Qing Dao) Ltd.
- Inventors: DEOK-YONG KIM; YONGCHUL OH
- Web page: https://patentgrep.com/patent/US20210280412A1

## CPC

- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10P 14/63: {characterised by the formation processes}
- H10B 12/482: {Bit lines}
- H10D 64/01306: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon}
- H10D 64/0132: {the conductor being a metallic silicide}
- H10P 14/66: {characterised by the type of materials}
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 70/65: Shapes or dispositions of interconnections
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor component includes a semiconductor substrate, a first oxide layer, an oxide, a first polysilicon layer, a first metal layer, a first mask on the first metal layer, and a bitline. The semiconductor substrate includes an array region, a periphery region and a boundary open region. The boundary open region isolates the array region from the periphery region. The first oxide layer is deposited on the array region. The first polysilicon layer is deposited on the periphery region. The first metal layer is deposited on the first polysilicon layer. A trench is formed on the array region and passes through the first oxide layer. The bitline includes a second polysilicon layer filling in the trench and a second metal layer on the second polysilicon layer. A second mask is formed on the second metal layer. The second polysilicon layer is flush with the first oxide layer.

## Claims

### Claim 1

A method for fabricating a semiconductor component comprising:
providing a semiconductor substrate comprising an array region, a periphery region and a boundary open region isolating the array region from the periphery region;
depositing a first oxide layer on the array region;
depositing a first polysilicon layer on the semiconductor substrate to cover the first oxide layer, the periphery region and the boundary open region;
depositing a second oxide layer on the first polysilicon layer;
removing a portion of the second oxide layer on the array region and the boundary open region, and removing a portion of the first polysilicon layer on the array region and the boundary open region;
forming a trench on the array region, wherein the trench passing through the first oxide layer;
depositing a second polysilicon layer to cover the first oxide layer, the trench, the boundary open region, and a remaining portion of the second oxide layer on the periphery region, the second polysilicon filling the trench;
removing a portion of the second polysilicon layer outside the trench, and removing the remaining portion of the second oxide layer on the periphery region;
depositing a metal layer to cover the first oxide layer, a remaining portion of the second polysilicon layer in the trench, the boundary open region, and a remaining portion of the first polysilicon layer on the periphery region;
forming a mask on the metal layer, wherein a portion of the metal layer on the boundary open region is exposed from the mask;
forming an opening to expose the boundary open region by etching the portion of the metal layer on the boundary open region;
depositing an oxide in the opening; and
exposing the first oxide layer and forming a bitline corresponding to the trench by an etching process.

### Claim 2 (depends on 1)

The method of claim 1, wherein a width of the bitline is less than a width of the trench.

### Claim 3 (depends on 2)

The method of claim 2, wherein the bitline is separated from a side wall of the trench.

### Claim 4 (depends on 1)

The method of claim 1, wherein a surface of a portion of the mask on the bitline facing away from the semiconductor substrate is flush with a surface of a portion of the mask on the periphery region facing away from the semiconductor substrate.

### Claim 5 (depends on 4)

The method of claim 4, wherein a surface of the first oxide layer facing away from the semiconductor substrate is flush with a surface of the remaining portion of the first polysilicon layer facing away from the semiconductor substrate.

### Claim 6 (depends on 1)

The method of claim 1, wherein a surface of the first oxide layer facing away from the semiconductor substrate is flush with a surface of the remaining portion of the first polysilicon layer facing away from the semiconductor substrate.

### Claim 7 (depends on 1)

The method of claim 1, wherein a method of removing the portion of the second polysilicon layer outside the trench, and removing the remaining portion of the second oxide layer on the periphery region comprises:
removing a portion of the second polysilicon layer outside the trench by dry etching;
forming a photoresist layer on the first oxide layer and the remaining portion of the second oxide layer on the periphery region, wherein the boundary open region is exposed from the photoresist layer;
removing a remaining portion of the second polysilicon layer on the boundary open region by dry etching; and
removing the remaining portion of the second oxide layer on the periphery region by wet etching.

### Claim 8 (depends on 1)

The method of claim 1, wherein the metal layer is made of a material selected from tungsten, tungsten silicide, titanium, and titanium silicide.

### Claim 9 (depends on 1)

The method of claim 1, wherein the mask is made of nitride.

### Claim 10 (depends on 1)

The method of claim 1, wherein after depositing the oxide in the opening and before the etching process, the method further comprises:
executing a chemical mechanical polishing process for planarization of the deposited oxide.

### Claim 11 (depends on 1)

The method of claim 1, wherein the trench is formed by etching or mechanical cutting.

### Claim 12 (depends on 1)

The method of claim 1, wherein the portion of the second oxide layer on the array region and the boundary open region and the portion of the first polysilicon layer on the array region and the boundary open region are removed by dry etching.

### Claim 13

A semiconductor component comprising:
a semiconductor substrate comprising an array region, a periphery region and a boundary open region isolating the array region from the periphery region;
a first oxide layer on the array region;
an oxide on the boundary open region;
a first polysilicon layer on the periphery region;
a first metal layer on the first polysilicon layer;
a first mask on the first metal layer; and
a bitline;
wherein a trench is formed on the array region and passes through the first oxide layer, the bitline comprises a second polysilicon layer filling in the trench and a second metal layer on the second polysilicon layer; a second mask is formed on the second metal layer; a surface of the second polysilicon layer facing away from the semiconductor substrate is flush with a surface of the first oxide layer facing away from the semiconductor substrate.

### Claim 14 (depends on 13)

The semiconductor component of claim 13, wherein a width of the bitline is less than a width of the trench.

### Claim 15 (depends on 14)

The semiconductor component of claim 14, wherein the bitline is separated from a side wall of the trench.

### Claim 16 (depends on 13)

The semiconductor component of claim 13, wherein a surface of the second mask facing away from the semiconductor substrate is flush with a surface of the first mask facing away from the semiconductor substrate.

### Claim 17 (depends on 16)

The semiconductor component of claim 16, wherein a surface of the first oxide layer facing away from the semiconductor substrate is flush with a surface of the first polysilicon layer facing away from the semiconductor substrate.

### Claim 18 (depends on 13)

The semiconductor component of claim 13, wherein the first metal layer is made of a material selected from tungsten, tungsten silicide, titanium, and titanium silicide.

### Claim 19 (depends on 13)

The semiconductor component of claim 13, wherein the second metal layer is made of a material selected from tungsten, tungsten silicide, titanium, and titanium silicide.

### Claim 20 (depends on 13)

The semiconductor component of claim 13, wherein each of the first mask and the second mask is made of nitride.