# US 2021/0280267 A1 · Configurable Soft Post-Package Repair (SPPR) Schemes

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- Number: US 2021/0280267 A1
- Document ID: US20210280267A1
- Status: Published application
- Kind: A1
- Application number: 16/811,691
- Filed: 2020-03-06
- Published: 2021-09-09
- Earliest claimed: 2020-03-06
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Gary Howe; John E. Riley
- Web page: https://patentgrep.com/patent/US20210280267A1

## CPC

- G11C 29/4401: {for self repair}
- G11C 17/16: using electrically-fusible links
- G11C 17/18: Auxiliary circuits, e.g. for writing into memory
- G11C 29/38: Response verification devices
- G11C 29/76: {using address translation or modifications}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Systems and methods to perform multiple row repair mode for soft post-packaging repair of previously repaired data groups are disclosed. The devices may have activation circuitry that includes a mode register bit or a control antifuse that sends an input signal upon activation. The devices may also include a logic element that receives the input signal and sends, upon receiving the input signal, a configuration signal that enables a multiple row repair mode.

## Claims

### Claim 1

A memory device comprising:
activation circuitry comprising a mode register bit or a control antifuse configured to send an input signal upon activation; and
a logic element configured to:
receive the input signal; and
send, upon receiving the input signal, a configuration signal, wherein the configuration signal enables a multiple row repair mode.

### Claim 2 (depends on 1)

The memory device of claim 1, further comprising:
SPPR circuitry configured to:
receive the configuration signal, wherein the configuration signal provides a plurality of address rows;
enter the multiple row repair mode to repair the provided plurality of address rows; and
compare a plurality of stored address rows to the provided plurality of address rows.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the mode register bit and the control antifuse connect to the logic element via input terminals on the logic element.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein the mode register bit alternates between single row replacement and multiple row replacement via a switch.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the mode register bit alternates between single row replacement and multiple row replacement via a command entry.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the mode register bit alternates between single or multiple row replacement for soft post-package repair (SPPR).

### Claim 7 (depends on 6)

The memory device of claim 6, wherein the SPPR repairs a single address and the HPPR repairs multiple addresses.

### Claim 8

A method for soft post-package repair (SPPR) comprising:
sending, via activation circuitry, an input signal from a mode register bit or an antifuse to a logic element;
sending, via the logic element after receiving the input signal, a configuration signal to SSPR circuitry; and
enabling, via the SSPR circuitry and after receiving the configuration signal, a multiple row address repair mode.

### Claim 9 (depends on 8)

The method of claim 8, wherein the configuration signal is a logic high signal.

### Claim 10 (depends on 8)

The method of claim 8, the multiple row address repair mode compares a plurality of provided addresses to a plurality of stored addresses, and wherein the plurality of provided addresses is determined by the configuration signal.

### Claim 11 (depends on 8)

The method of claim 8, wherein the mode register bit sends the input signal after receiving a command entry.

### Claim 12 (depends on 8)

The method of claim 8, wherein the mode register bit sends the input signal after being activated via a switch.

### Claim 13 (depends on 8)

The method of claim 8, wherein the antifuse is blown to send the input signal.

### Claim 14

A memory device, comprising:
a memory bank comprising a plurality of addressable groups of memory cells, wherein the plurality of addressable groups of memory cells comprises a primary set of addressable groups and a secondary set of addressable groups; and
control circuitry configured to activate an addressable group of the plurality of addressable groups, the control circuitry comprising:
first repair circuitry comprising a first non-volatile memory configured to store a first set of addresses corresponding to a first defective addressable group of the plurality of addressable groups repaired in a first mode;
second repair circuitry comprising a second non-volatile memory configured to store a second set of addresses corresponding to a second defective addressable group of the plurality of addressable groups repaired in a second mode;
activation circuitry comprising a mode register bit or a control antifuse configured to send an input signal upon activation; and
a logic element configured to:
receive the input signal; and
send, upon receiving the input signal, a configuration signal, wherein the configuration signal enables a multiple row repair mode of the first defective addressable group or the second defective addressable group.

### Claim 15 (depends on 14)

The memory device of claim 14, wherein the mode register bit and the control antifuse connect to the logic element via input terminals on the logic element.

### Claim 16 (depends on 14)

The memory device of claim 14, wherein the mode register bit alternates between single row testing and multiple row testing via a switch.

### Claim 17 (depends on 14)

The memory device of claim 14, wherein the mode register bit alternates between single row testing and multiple row testing via a command entry.

### Claim 18 (depends on 14)

The memory device of claim 14, further comprising:
SPPR circuitry configured to:
receive the configuration signal, wherein the configuration signal provides a plurality of address rows;
enter the multiple row repair mode to repair the provided plurality of address rows; and
compare the first defective group or the second defective group to the provided plurality of address rows.

### Claim 19 (depends on 18)

The memory device of claim 18, wherein the SPPR circuitry comprises a plurality of logic elements, and wherein each logic element of the plurality of logic elements compares a provided address row from the plurality of address rows to a defective address row of the first defective group or the second defective group.

### Claim 20 (depends on 18)

The memory device of claim 18, wherein the configuration signal enables the SPPR circuitry to repair the plurality of address rows as a hard post-package repair.

### Claim 21 (depends on 14)

The memory device of claim 14, wherein the control circuitry comprises third repair circuitry comprising a volatile memory configured to store an address corresponding to a third defective addressable group repaired in a soft post-packaging repair, and wherein the logic element is configured to compare a received address with the address stored in the volatile memory.