# US 2021/0280265 A1 · Memory circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0280265 A1 - Document ID: US20210280265A1 - Status: Published application - Kind: A1 - Application number: 17/250,417 - Filed: 2019-07-25 - Published: 2021-09-09 - Earliest claimed: 2018-07-30 - Assignees: Sony Semiconductor Solutions Corporation - Applicants: Sony Semiconductor Solutions Corporation - Inventors: HIROYUKI TEZUKA; MASAMI KURODA - Web page: https://patentgrep.com/patent/US20210280265A1 ## CPC - G11C 29/24: Accessing extra cells, e.g. dummy cells or redundant cells - G11C 7/14: Dummy cell management; Sense reference voltage generators - G11C 11/1673: {Reading or sensing circuits or methods} - G11C 11/2273: {Reading or sensing circuits or methods} - G11C 13/004: {Reading or sensing circuits or methods} - G11C 29/022: {in I/O circuitry} - G11C 29/12005: {comprising voltage or current generators} - G11C 29/18: Address generation devices; Devices for accessing memories, e.g. details of addressing circuits - G11C 29/46: Test trigger logic - G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell} - G11C 2029/1202: {Word line control} - G11C 2029/1204: {Bit line control} - G11C 2029/1802: {Address decoder} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The reference cells used for reading out data are tested efficiently so as to improve the reliability of the readout data. A memory circuit includes multiple memory arrays, a selection circuit, and a sense amplifier. The selection circuit selects values output from memory cells in any of the multiple memory arrays so as to supply a first value and a second value. A sense amplifier has a first input terminal and a second input terminal. The sense amplifier amplifies and outputs the first value supplied to the first input terminal in reference to the second value supplied to the second input terminal. ## Claims ### Claim 1 A memory circuit comprising: multiple memory arrays; a selection circuit configured to select values output from memory cells in any of the multiple memory arrays, so as to supply a first value and a second value; and a sense amplifier that has a first input terminal and a second input terminal and that is configured to amplify and output the first value supplied to the first input terminal in reference to the second value supplied to the second input terminal. ### Claim 2 (depends on 1) The memory circuit according to claim 1, wherein the selection circuit includes multiple output switches provided corresponding to each of the memory cells, the output switches being configured to control whether or not to output the value from each corresponding memory cell, and a first input selector and a second input selector provided corresponding to the first input terminal and the second input terminal of the sense amplifier, respectively, the first input selector and the second input selector being configured to select output from the output switches and supply the selected output to the corresponding first and second input terminals. ### Claim 3 (depends on 2) The memory circuit according to claim 2, wherein each of the first and second input selectors is provided with multiple input switches connected to the output of one or more mutually different output switches among the multiple output switches, each of the first and the second input selectors being configured to let any one of the multiple input switches conduct to supply the output therefrom to the corresponding first and second input terminals. ### Claim 4 (depends on 3) The memory circuit according to claim 3, wherein at least one of the multiple input switches receives, in a short-circuited state, the output of the multiple output switches connected to each of the input switches. ### Claim 5 (depends on 4) The memory circuit according to claim 4, wherein the number of the multiple output switches connected to each of the multiple input switches is the same. ### Claim 6 (depends on 4) The memory circuit according to claim 4, wherein the number of the multiple output switches connected to each of the multiple input switches is at least partially different. ### Claim 7 (depends on 1) The memory circuit according to claim 1, further comprising: a plurality of the sense amplifiers sharing the second input terminal. ### Claim 8 (depends on 1) The memory circuit according to claim 1, wherein the memory cell includes a resistance change memory. ### Claim 9 (depends on 1) The memory circuit according to claim 1, wherein the memory cell includes a magnetic resistance change memory. ### Claim 10 (depends on 1) The memory circuit according to claim 1, wherein the sense amplifier performs a process of outputting data reflecting a magnitude relation between a first potential and a second potential supplied respectively to the first input terminal and the second input terminal, and a process of outputting data reflecting a magnitude relation between a third potential and a fourth potential supplied respectively to the first input terminal and the second input terminal, the third potential being used to generate the second potential, the fourth potential being different from the second potential. ### Claim 11 (depends on 10) The memory circuit according to claim 10, wherein the second potential is a reference potential for reading out the first potential, and the fourth potential is a reference potential for testing the third potential. ### Claim 12 (depends on 10) The memory circuit according to claim 10, wherein the first potential and the second potential are read out from mutually different memory arrays among the multiple memory arrays, and the third potential and the fourth potential are read out from a same memory array. ### Claim 13 (depends on 10) The memory circuit according to claim 10, wherein the sense amplifier outputs the data in a case where the first potential and the second potential are supplied respectively to the first input terminal and the second input terminal and outputs the data in a case where the third potential and the fourth potential are supplied respectively to the first input terminal and the second input terminal, at different timings. ### Claim 14 (depends on 10) The memory circuit according to claim 10, wherein the sense amplifier outputs the data in a case where the first potential and the second potential are supplied respectively to the first input terminal and the second input terminal and outputs the data in a case where the third potential and the fourth potential are supplied respectively to the first input terminal and the second input terminal, at a same timing. ### Claim 15 (depends on 10) The memory circuit according to claim 10, further comprising: a comparator configured to compare the output in a case where the third potential and the fourth potential are supplied respectively to the first input terminal and the second input terminal, with a value expected of the output.