# US 2021/0280264 A1 · Memory system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0280264 A1 - Document ID: US20210280264A1 - Status: Published application - Kind: A1 - Application number: 17/173,446 - Filed: 2021-02-11 - Published: 2021-09-09 - Earliest claimed: 2020-03-03 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Prashob RAMACHANDRAN NAIR - Web page: https://patentgrep.com/patent/US20210280264A1 ## CPC - G11C 29/24: Accessing extra cells, e.g. dummy cells or redundant cells - G11C 29/42: using error correcting codes [ECC] or parity check - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/3431: {Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step} - G11C 29/04: Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals} - G11C 29/12015: {comprising clock generation or timing circuitry} - G11C 29/36: Data generation devices, e.g. data inverters - G11C 29/38: Response verification devices - G11C 2029/0409: {Online test} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory system includes a nonvolatile semiconductor memory and a memory controller. The memory controller is configured to schedule plural types of reliability countermeasure processes to be executed for the nonvolatile semiconductor memory. The plural types of reliability countermeasure processes includes at least a first reliability countermeasure process. The memory controller is configured to skip the first reliability countermeasure process to be executed when the first reliability countermeasure process is not necessary to be executed by executing an access process other than the first reliability countermeasure process to the nonvolatile semiconductor memory. ## Claims ### Claim 1 A memory system comprising: a nonvolatile semiconductor memory; and a memory controller configured to: schedule plural types of reliability countermeasure processes to be executed for the nonvolatile semiconductor memory, the plural types of reliability countermeasure processes including at least a first reliability countermeasure process; and skip the first reliability countermeasure process to be executed when the first reliability countermeasure process is not necessary to be executed by executing an access process other than the first reliability countermeasure process to the nonvolatile semiconductor memory. ### Claim 2 (depends on 1) The memory system according to claim 1, wherein the memory controller is configured to: manage a time stamp table containing the latest execution time of each of the plural types of reliability countermeasure processes; and determine whether or not to execute one of the plural types of reliability countermeasure processes based on the execution time recorded in the time stamp table. ### Claim 3 (depends on 2) The memory system according to claim 2, wherein the memory controller is configured to: compare a current time with the latest execution time of the one of the plural types of reliability countermeasure processes scheduled to be executed; and execute the one of the plural types of reliability countermeasure processes scheduled to be executed, when a difference between the current time and the latest execution time is equal to or greater than a predetermined time limit. ### Claim 4 (depends on 3) The memory system according to claim 3, wherein the predetermined time limit is defined for each type of the reliability countermeasure. ### Claim 5 (depends on 3) The memory system according to claim 3, wherein the memory controller is further configured to: in a case where an effect of the first reliability countermeasure process is achieved by executing the access process, update the latest execution time of the first reliability countermeasure process to a time of completion of the execution of the access process, and skip the first reliability countermeasure process when a difference between the current time and the updated latest execution time of the first reliability countermeasure process is smaller than the predetermined time limit. ### Claim 6 (depends on 5) The memory system according to claim 5, wherein the memory controller is further configured to communicate with a host, the nonvolatile semiconductor memory includes a memory cell array, the plural types of reliability countermeasure processes further include a host read operation and a dummy read operation, the host read operation being an operation in which data is read from the memory cell array and output to the host via the memory controller, the dummy read operation being an operation in which data is read from the memory cell array but not output to the memory controller, and the memory controller is configured to: in response to the host read operation being executed, update the latest execution time of the dummy read operation to a time of completion of the host read operation, and in response to the dummy read operation being executed, keep the latest execution time of the host read operation as it is. ### Claim 7 (depends on 5) The memory system according to claim 5, wherein the nonvolatile semiconductor memory includes a memory cell array, the plural types of reliability countermeasure processes further include a patrol read operation and a dummy read operation, the patrol read operation being an operation in which data is read from the memory cell array and an error correction process is performed on the read data, the dummy read operation being an operation in which data is read from the memory cell array but the error correction process is not performed on the read data, and the memory controller is configured to: in response to the patrol read operation being executed, update the latest execution time of the dummy read operation to a time of completion of the patrol read operation, and in response to the dummy read operation being executed, keep the latest execution time of the patrol read operation as it is. ### Claim 8 (depends on 5) The memory system according to claim 5, wherein the memory controller is configured to: manage a bitmap table containing a bit value for each type of the reliability countermeasure process, the bit value indicating whether or not each of the plural types of reliability countermeasure processes is required to be executed; and determine whether or not to execute one of the plural types of reliability countermeasure processes based on the bit value recorded in the bitmap table. ### Claim 9 (depends on 8) The memory system according to claim 8, wherein the nonvolatile semiconductor memory includes a plurality of blocks, each of the plurality of blocks including a plurality of pages and being a unit of an erase operation, and the memory controller is configured to in response to the erase operation being executed to a first block, reset the bit value for each type of the reliability countermeasure process for each of the plurality of pages included in the first block. ### Claim 10 (depends on 8) The memory system according to claim 8, wherein the nonvolatile semiconductor memory includes a plurality of blocks, each of the plurality of blocks including a plurality of pages, and the memory controller is configured to in response to a first block becoming a defective block, reset the bit value for each type of the reliability countermeasure process for each of the plurality of pages included in the first block. ### Claim 11 A method of controlling a nonvolatile semiconductor memory, the method comprising: scheduling plural types of reliability countermeasure processes to be executed for the nonvolatile semiconductor memory, the plural types of reliability countermeasure processes including at least a first reliability countermeasure process; and skipping the first reliability countermeasure process to be executed when the first reliability countermeasure process is not necessary to be executed by executing an access process other than the first reliability countermeasure process to the nonvolatile semiconductor memory. ### Claim 12 (depends on 11) The method according to claim 11, further comprising: managing a time stamp table containing the latest execution time of each of the plural types of reliability countermeasure processes; and determining whether or not to execute one of the plural types of reliability countermeasure processes based on the execution time recorded in the time stamp table. ### Claim 13 (depends on 12) The method according to claim 12, further comprising: comparing a current time with the latest execution time of the one of the plural types of reliability countermeasure processes scheduled to be executed; and executing the one of the plural types of reliability countermeasure processes scheduled to be executed, when a difference between the current time and the latest execution time is equal to or greater than a predetermined time limit. ### Claim 14 (depends on 13) The method according to claim 13, wherein the predetermined time limit is defined for each type of the reliability countermeasure. ### Claim 15 (depends on 13) The method according to claim 13, further comprising: in a case where an effect of the first reliability countermeasure process is achieved by executing the access process, updating the latest execution time of the first reliability countermeasure process to a time of completion of the execution of the access process, and skipping the first reliability countermeasure process when a difference between the current time and the updated latest execution time of the first reliability countermeasure process is smaller than the predetermined time limit. ### Claim 16 (depends on 15) The method according to claim 15, wherein the nonvolatile semiconductor memory includes a memory cell array, the plural types of reliability countermeasure processes further include a host read operation and a dummy read operation, the host read operation being an operation in which data is read from the memory cell array and output to a host, the dummy read operation being an operation in which data is read from the memory cell array but not output to the host, and wherein the method further comprises: in response to the host read operation being executed, updating the latest execution time of the dummy read operation to a time of completion of the host read operation, and in response to the dummy read operation being executed, keeping the latest execution time of the host read operation as it is. ### Claim 17 (depends on 15) The method according to claim 15, wherein the nonvolatile semiconductor memory includes a memory cell array, the plural types of reliability countermeasure processes further include a patrol read operation and a dummy read operation, the patrol read operation being an operation in which data is read from the memory cell array and an error correction process is performed on the read data, the dummy read operation being an operation in which data is read from the memory cell array but the error correction process is not performed on the read data, and the method further comprises: in response to the patrol read operation being executed, updating the latest execution time of the dummy read operation to a time of completion of the patrol read operation, and in response to the dummy read operation being executed, keeping the latest execution time of the patrol read operation as it is. ### Claim 18 (depends on 15) The method according to claim 15, further comprising: managing a bitmap table containing a bit value for each type of the reliability countermeasure process, the bit value indicating whether or not each of the plural types of reliability countermeasure processes is required to be executed; and determining whether or not to execute one of the plural types of reliability countermeasure processes based on the bit value recorded in the bitmap table. ### Claim 19 (depends on 18) The method according to claim 18, wherein the nonvolatile semiconductor memory includes a plurality of blocks, each of the plurality of blocks including a plurality of pages and being a unit of an erase operation, and the method further comprises in response to the erase operation being executed to a first block, resetting the bit value for each type of the reliability countermeasure process for each of the plurality of pages included in the first block. ### Claim 20 (depends on 18) The method according to claim 18, wherein the nonvolatile semiconductor memory includes a plurality of blocks, each of the plurality of blocks including a plurality of pages, and the method further comprises in response to a first block becoming a defective block, resetting the bit value for each type of the reliability countermeasure process for each of the plurality of pages included in the first block.